A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Miura, Noriyuki ^a   Mizoguchi, Daisuke ^a   Inoue, Mari ^a   Tsuji, Hiroo ^a   Sakurai, Takayasu ^b   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844471777     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. Ezaki et al., "A 160Gb/s Interface Design Configuration for Multichip LSI," ISSCC Dig. Tech. Papers, pp.140-141, Feb., 2004.
2. D. Mizoguchi et al., "A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-cihp Signaling (IIS)," ISSCC Dig. Tech. Papers, pp.142-143, Feb., 2004.
3. N. Miura et al., "Cross Talk Countermeasures in Inductive Inter-chip Wireless Superconnect," Proc. CICC, pp.99-102, Oct., 2004.
4. T. Ohguro et al., "Ultra-Thin Chip with Permalloy Film for High Performance MS/RF CMOS," Symp. VLSI Technology, pp.220-221, June, 2004.