Statistical circuit optimization considering device andinterconnect process variations

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2007, Pages 47-54

  Lin, I Jye ^a   Ling, Tsui Yee ^a   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Gate and wire sizing; Statistical optimization

Indexed keywords

ALGORITHMS; ELECTRIC POWER UTILIZATION; ELECTROMIGRATION; OPTIMIZATION; PROBLEM SOLVING; STATISTICAL METHODS;

INTEGRATION DENSITY; INTERCONNECT DELAY; PROCESS VARIATION; STATISTICAL OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 34748849452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231956.1231966     Document Type: Conference Paper

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