Analysis and optimization of thermal issues in high-performance VLSI

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2001, Pages 230-237

  Banerjee, K ^a   Pedram, M ^a   Ajami, A H ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; HEAT SINKS; OPTIMIZATION; SEMICONDUCTING SILICON; SUBSTRATES; THERMAL EFFECTS;

ELECTROTHERMAL MODELS;

VLSI CIRCUITS;

EID: 0034819419     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/369691.369779     Document Type: Conference Paper

References (33)

1. Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
2. Thermal effects in deep sub-micron VLSI interconnects
3. Electromigration - A brief survey and some recent results
4. Projecting interconnect electromigration lifetime for arbitrary current waveforms
5. High-current failure model for VLSI interconnects under short-pulse stress conditions
6. Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions
7. Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS
8. Air-Gap formation during ILD deposition to lower interconnect capacitance
9. The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal
10. A practical repeater insertion method in high speed VLSI circuits
11. On thermal effects in deep sub-micron VLSI interconnects
12. Quantitative projections of reliability and performance for low-k/Cu interconnect systems
13. Thermal analysis of electromigration test structures
14. Self-consistent solutions for allowed interconnect current density - Part I: Implications for technology evolution
15. Self-consistent solutions for allowed interconnect current density - Part II: Application to design guidelines
16. Heat conduction in novel electronic films
17. Planning for performance
18. The transient response of damped linear network with particular regard to wide-band amplifier
19. Analysis of non-uniform temperature-dependent interconnect performance in high-performance ICs
20. Optimal wire-sizing formula under the Elmore delay model
21. Zero skew clock routing with minimum wirelength
22. Characterization and modeling of clock skew with process variation
23. Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs
24. Non-uniform chip-temperature dependent signal integrity
25. ESD: A pervasive reliability concern for IC technologies
26. State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs
27. ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology
28. Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects