A trace cache microarchitecture and evaluation

IEEE Transactions on Computers

Volumn 48, Issue 2, 1999, Pages 111-120

  Rotenberg, Eric ^b   Bennett, Steve ^a,c   Smith, James E ^a,d  

^a IEEE

^b University of Wisconsin Madison   (United States)

^c INTEL CORPORATION   (United States)

^d University of Wisconsin Madison   (United States)

Author keywords

Instruction cache; Instruction fetching; Multiple branch prediction; Superscalar processors; Trace cache

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS);

INSTRUCTION CACHE; INSTRUCTION FETCHING; MULTIPLE BRANCHH PREDICTION; TRACE CACHE MICROARCHITECTURE;

BUFFER STORAGE;

EID: 0033077095     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.752652     Document Type: Review

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