Reconsidering complex branch predictors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 43-52

  Jimenez, D A ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

Arithmetic; Clocks; Computer science; Delay; Hardware; Microarchitecture; Microprocessors; Pipelines; Random access memory; Throughput

Indexed keywords

BUDGET CONTROL; CLOCKS; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; DIGITAL ARITHMETIC; HARDWARE; MICROPROCESSOR CHIPS; PIPELINES; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE; SUPERCOMPUTERS; THROUGHPUT;

BRANCH PREDICTORS; CHIP DENSITY; DELAY; MICRO ARCHITECTURES; PERFORMANCE BENEFITS; PREDICTOR DESIGN; RANDOM ACCESS MEMORY; THROUGHPUT RATE;

COMPUTER HARDWARE;

EID: 71049193515     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183523     Document Type: Conference Paper

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