A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

ACM Transactions on Architecture and Code Optimization

Volumn 1, Issue 2, 2004, Pages 220-245

  Santana, Oliverio J ^a   Ramirez, Alex ^a   Larriba Pey, Josep L ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Branch prediction; Design; Fetch architecture; High performance; Instruction stream; Low complexity; Performance

Indexed keywords

EID: 33646373633     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1011528.1011532     Document Type: Article

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