-
1
-
-
27344456043
-
The Æthereal network on chip: Concepts, architectures, and implementations
-
Sept-Oct
-
Kees Goossens, John Dielissen, and Andrei Rǎdulescu. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5):21-31, Sept-Oct 2005.
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
, pp. 21-31
-
-
Goossens, K.1
Dielissen, J.2
Rǎdulescu, A.3
-
2
-
-
77957961901
-
Practical design of globally-asynchronous locally-synchronous systems
-
Eilat, Israel, April
-
Jens Muttersbach, Thomas Villiger, and Wolfgang Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In Proceedings Intnl. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 52-59, Eilat, Israel, April 2000.
-
(2000)
Proceedings Intnl. Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC)
, pp. 52-59
-
-
Muttersbach, J.1
Villiger, T.2
Fichtner, W.3
-
5
-
-
0003780621
-
-
Jens Sparsø and Steve Furber, editors, Kluwer Academic Publishers, Dordrecht, The Netherlands, September
-
Jens Sparsø and Steve Furber, editors. Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, Dordrecht, The Netherlands, September 2001.
-
(2001)
Principles of Asynchronous Circuit Design: A Systems Perspective
-
-
-
6
-
-
0035186879
-
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
-
Austin, TX, USA, September
-
Montek Singh and Steven M. Nowick. MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. In Proceedings International Conference on Computer Design (ICCD), pages 9-17, Austin, TX, USA, September 2001.
-
(2001)
Proceedings International Conference on Computer Design (ICCD)
, pp. 9-17
-
-
Singh, M.1
Nowick, S.M.2
-
7
-
-
0034431019
-
Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5 GHz
-
San Francisco, CA, USA, February
-
S. Schuster et al. Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5 GHz. In Proceedings International Solid State Circuits Conference (ISSCC), pages 292-293, San Francisco, CA, USA, February 2000.
-
(2000)
Proceedings International Solid State Circuits Conference (ISSCC)
, pp. 292-293
-
-
Schuster, S.1
-
8
-
-
77957951588
-
GasP: A Minimal FIFO Control
-
Salt Lake City, UT, USA, March
-
Ivan Sutherland and Scott Fairbanks. GasP: A Minimal FIFO Control. In Proceedings Intnl. Symposium on Advanced Research in Asynchronous and Systems (ASYNC), pages 46-53, Salt Lake City, UT, USA, March 2001.
-
(2001)
Proceedings Intnl. Symposium on Advanced Research in Asynchronous and Systems (ASYNC)
, pp. 46-53
-
-
Sutherland, I.1
Fairbanks, S.2
-
10
-
-
84961967572
-
Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications
-
Orlando, FL, USA, April
-
Montek Singh and Steven M. Nowick. Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications. In Proceedings of the IEEE Computer Society Workshop on VLSI, pages 111-118, Orlando, FL, USA, April 2000.
-
(2000)
Proceedings of the IEEE Computer Society Workshop on VLSI
, pp. 111-118
-
-
Singh, M.1
Nowick, S.M.2
-
11
-
-
0030394758
-
A Parametric Design of a Built-in Self Test FIFO Embedded Memory
-
Boston, MA, USA, November
-
S. Barbagallo et al. A Parametric Design of a Built-in Self Test FIFO Embedded Memory. In Proceedings IEEE Intnl. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pages 221-229, Boston, MA, USA, November 1996.
-
(1996)
Proceedings IEEE Intnl. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)
, pp. 221-229
-
-
Barbagallo, S.1
-
12
-
-
28444467190
-
Functional Test for Shifting-Type FIFOs
-
Paris, France, March
-
Ad J. van de Goor, Ivo Schanstra, and Yervant Zorian. Functional Test for Shifting-Type FIFOs. In Proceedings European Design and Test Conference (ED&TC), pages 133-138, Paris, France, March 1995.
-
(1995)
Proceedings European Design and Test Conference (ED&TC)
, pp. 133-138
-
-
van de Goor, A.J.1
Schanstra, I.2
Zorian, Y.3
-
13
-
-
0004172854
-
An Effective BIST Scheme for Ring-Address Type FlFOs
-
Washington, DC, USA, October
-
Yervant Zorian, Ad J. van de Goor, and Ivo Schanstra. An Effective BIST Scheme for Ring-Address Type FlFOs. In Proceedings IEEE International Test Conference (ITC), pages 378-387, Washington, DC, USA, October 1994.
-
(1994)
Proceedings IEEE International Test Conference (ITC)
, pp. 378-387
-
-
Zorian, Y.1
van de Goor, A.J.2
Schanstra, I.3
-
14
-
-
28444461050
-
Methodologies and Algorithms for Testing SwitchBased NoC Interconnects
-
Monterey, CA, USA, October
-
Cristian Grecu et al. Methodologies and Algorithms for Testing SwitchBased NoC Interconnects. In Proceedings IEEE Intnl. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pages 238-246, Monterey, CA, USA, October 2005.
-
(2005)
Proceedings IEEE Intnl. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)
, pp. 238-246
-
-
Grecu, C.1
-
15
-
-
18144374601
-
Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories
-
Charlotte, NC, USA, October
-
Rob Aitken. A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. In Proceedings IEEE International Test Conference (ITC), pages 997-1005, Charlotte, NC, USA, October 2004.
-
(2004)
Proceedings IEEE International Test Conference (ITC)
, pp. 997-1005
-
-
Rob Aitken, A.1
-
16
-
-
0033326303
-
Practical Scan Test Generation and Application for Embedded FIFOs
-
Atlantic City, NJ, USA, September
-
Jeff Rearick. Practical Scan Test Generation and Application for Embedded FIFOs. In Proceedings IEEE International Test Conference (ITC), pages 294-300, Atlantic City, NJ, USA, September 1999.
-
(1999)
Proceedings IEEE International Test Conference (ITC)
, pp. 294-300
-
-
Rearick, J.1
-
17
-
-
33847118892
-
Test Generation for Ultra-High-Speed Asynchronous Pipelines
-
Austin, TX, USA, November
-
Feng Shi, Yiorgos Makris, Steven M. Nowick, and Montek Singh. Test Generation for Ultra-High-Speed Asynchronous Pipelines. In Proceedings IEEE International Test Conference (ITC), pages 1009-1018, Austin, TX, USA, November 2005.
-
(2005)
Proceedings IEEE International Test Conference (ITC)
, pp. 1009-1018
-
-
Shi, F.1
Makris, Y.2
Nowick, S.M.3
Singh, M.4
-
18
-
-
34548321156
-
-
Tobias Dubois, Mohamed Azimane, Erik Larsson, Erik Jan Marinissen, Paul Wielage, and Clemens Wouters. Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO. In Proceedings Design, Automation, and Test in Europe (DATE), Nice, France, April 2007.
-
Tobias Dubois, Mohamed Azimane, Erik Larsson, Erik Jan Marinissen, Paul Wielage, and Clemens Wouters. Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO. In Proceedings Design, Automation, and Test in Europe (DATE), Nice, France, April 2007.
-
-
-
-
19
-
-
0022873558
-
Star. Macro Testing: Unifying IC and Board Test
-
December
-
Frans Beenker, Karel van Eerdewijk, Robert Gerritsen, Frank Peacock, and Max van der Star. Macro Testing: Unifying IC and Board Test. IEEE Design & Test of Computers, 3(4):26-32, December 1986.
-
(1986)
IEEE Design & Test of Computers
, vol.3
, Issue.4
, pp. 26-32
-
-
Beenker, F.1
van Eerdewijk, K.2
Gerritsen, R.3
Peacock, F.4
van der, M.5
-
20
-
-
0032306079
-
Testing EmbeddedCore Based System Chips
-
Washington, DC, USA, October
-
Yervant Zorian, Erik Jan Marinissen, and Sujit Dey. Testing EmbeddedCore Based System Chips. In Proceedings IEEE International Test Conference (ITC), pages 130-143, Washington, DC, USA, October 1998.
-
(1998)
Proceedings IEEE International Test Conference (ITC)
, pp. 130-143
-
-
Zorian, Y.1
Jan Marinissen, E.2
Dey, S.3
-
21
-
-
0032320505
-
A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores
-
Washington, DC, USA, October
-
Erik Jan Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proceedings IEEE International Test Conference (ITC), pages 284-293, Washington, DC, USA, October 1998.
-
(1998)
Proceedings IEEE International Test Conference (ITC)
, pp. 284-293
-
-
Jan Marinissen, E.1
-
22
-
-
0036575608
-
ETM10 Incorporates Hardware Segment of IEEE P1500
-
May/June
-
Teresa McLaurin and Souvik Ghosh. ETM10 Incorporates Hardware Segment of IEEE P1500. IEEE Design & Test of Computers, 19(3):6-11, May/June 2002.
-
(2002)
IEEE Design & Test of Computers
, vol.19
, Issue.3
, pp. 6-11
-
-
McLaurin, T.1
Ghosh, S.2
-
23
-
-
34548339058
-
-
Francisco DaSilva, editor, IEEE Standards Association, New York, NY, USA, August
-
Francisco DaSilva, editor. IEEE Std 1500™ -2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE Standards Association, New York, NY, USA, August 2005.
-
(2005)
IEEE Std 1500™ -2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
-
-
-
25
-
-
0030685592
-
Testing Embedded Cores Using Partial Isolation Rings
-
Monterey, CA, USA, April
-
Nur Touba and Bahram Pouya. Testing Embedded Cores Using Partial Isolation Rings. In Proceedings IEEE VLSI Test Symposium (VTS), pages 10-16, Monterey, CA, USA, April 1997.
-
(1997)
Proceedings IEEE VLSI Test Symposium (VTS)
, pp. 10-16
-
-
Touba, N.1
Pouya, B.2
-
26
-
-
0033316969
-
Towards a Standard for Embedded Core Test: An Example
-
Atlantic City, NJ, USA, September
-
Erik Jan Marinissen, Yervant Zorian, Rohit Kapur, Tony Taylor, and Lee Whetsel. Towards a Standard for Embedded Core Test: An Example. In Proceedings IEEE International Test Conference (ITC), pages 616-627, Atlantic City, NJ, USA, September 1999.
-
(1999)
Proceedings IEEE International Test Conference (ITC)
, pp. 616-627
-
-
Jan Marinissen, E.1
Zorian, Y.2
Kapur, R.3
Taylor, T.4
Whetsel, L.5
|