Parametric design of a built-in self-test FIFO embedded memory

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 221-229

  Barbagallo, S ^a   Bodoni Lobetti, M ^a   Medina, D ^a   De Blasio, G ^a   Ferloni, M ^a   Fummi, F ^a   Sciuto, D ^a  

^a DSRC ^*  (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CELLULAR ARRAYS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; SEMICONDUCTOR STORAGE;

BUILT IN SELF TEST (BIST); FIRST IN FIRST OUT (FIFO) MEMORIES;

RANDOM ACCESS STORAGE;

EID: 0030394758     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)