Test generation for ultra-high-speed asynchronous pipelines

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 1009-1018

  Shi, Feng ^a   Makris, Yiorgos ^a   Nowick, Steven M ^b   Singh, Montek ^c  

^a Yale University   (United States)

^b Columbia University ^*  (United States)

^c UNIVERSITY OF NORTH CAROLINA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DIGITAL CIRCUITS; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; NETWORK PROTOCOLS;

ASYNCHRONOUS CIRCUIT DESIGN; ASYNCHRONOUS PIPELINES; FUNCTIONAL CORRECTNESS; TIMING CONSTRAINTS;

PIPELINE PROCESSING SYSTEMS;

EID: 33847118892     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584067     Document Type: Conference Paper

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