On practical multiplexing issues

2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

Volumn 1, Issue , 2006, Pages 310-313

  Beiu, Valeriu ^a   Sulieman, Mawahib H ^a  

^a UNITED ARAB EMIRATES UNIVERSITY   (United Arab Emirates)

Author keywords

Fault tolerance; Multiplexing; Reliability; Single electron technology (SET)

Indexed keywords

CIRCUIT SIMULATION; FAULT TOLERANCE; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PROBABILITY; RELIABILITY THEORY;

ELEMENTARY GATES; SINGLE ELECTRON TECHNOLOGY (SET);

MULTIPLEXING;

EID: 34548245717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/nano.2006.247637     Document Type: Conference Paper

References (35)

1. C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, Jul.-Aug. 2003, pp. 14-19.
2. P. Sivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on soft error rate of combinatorial logic," Proc. Intl. Conf. Dependable Sys. & Networks DSN'02, Washington, DC, Jun. 2002, pp. 389-398.
3. P. Sivakumar, S.W. Keckler, CR. Moore, and D. Burger, "Exploiting microarchitectural redundancy for defect tolerance," Proc. Intl. Conf. Comp. Design ICCD '03, San Jose, CA, Oct. 2003, pp. 481-488.
4. International Technology Roadmap for Semiconductors, ITRS'2005. Available: public.itrs.net
5. V. Beiu, and U. Rückert, Emerging Brain Inspired Nano Architectures (book accepted for publication in 2005), World Scientific Press, in progress.
6. M. Forshaw, K. Nikolić, and A.S. Sadek, "ANSWERS: Autonomous Nanoelectronic Systems With Extended Replication and Signaling," MEL-ARl #28667. 3rd Year Report, 2001, pp. 1-32. Available: ipga.phys.ucl.ac.uk/ research/answers/reports/3rd_year_U_CL.pdf
7. K. Nikolić, A.S. Sadek, and M. Forshaw, "Fault-tolerant techniques for nanocomputers," Nanotechnology, vol. 13, Jun. 2002, pp. 357-362.
8. J. Han, and P. Jonker, "A system architecture solution for unreliable nanoelectronic devices," IEEE Trans. Nanotech., vol. 1, Dec. 2002, pp. 201-208.
9. J. Han, and P. Jonker, "A defect- and fault-tolerant architecture for nanocomputers," Nanotechnology, vol. 14, Feb. 2003, pp. 224-230.
10. A.S. Sadek, K. Nikolić, and M. Forshaw, "Parallel information and computation with restitution for noise-tolerant nanoscale logic networks," Nanotechnology, vol. 15, Jan. 2004, pp. 192-210.
11. S. Roy, and V. Beiu, "Majority multiplexing-Economical redundant fault-tolerant designs for nanoarchitectures," IEEE Trans. Nanotech., vol.4, Jul. 2005, pp. 441-451.
12. J. Han, J.B. Gao, P. Jonker, Y. Qi, and J.A.B. Fortes, "Toward hardware-redundant, fault-tolerant logic for nanoelectronics," IEEE Design & Test of Comp., vol. 22, Jul.-Aug. 2005, pp. 328-339.
13. J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in C. E. Shannon, and J. McCarthy (Eds.), Automata Studies, Princeton, NJ: Princeton Univ. Press, 1956, pp. 43-98.
14. J.R. Heath, P.J. Keukes, G.S. Snider, and R.S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, 280, Jun. 12, 1998, pp. 1716-1721.
15. S. Aunet, and M. Hartmann "Real-time reconfigurable threshold elements and some applications to neural hardware," Proc. Intl. Conf. Evolvable Sys. ICES'03, Trondheim, Norway, Springer LNCS 2606, Mar. 2003, pp. 365-376.
16. A. Schmid, and Y. Leblebici, "Robust circuit and system design methodologies for nanometer-scale devices and single electron transistors," Proc. IEEE-NANO'03, San Francisco, CA, Aug. 2003, vol.2, pp. 516-519.
17. F. Koushanfar, M. Potkonjak, and A. Sangiovanni-Vincentelli, "Fault tolerance techniques for wireless ad hoc sensor networks," Proc. IEEE Sensors, Orlando, FL, Jun. 2002, pp. 1491-1496.
18. W.S. Evans, "Information Theory and Noisy Computation," Ph.D. dissertation, ICSI Tech. Rep. TR-94-57, Berkeley, CA, Nov. 1994. Available: www.cs.ubc.ca/~will/papers/thesis.pdf
19. W.S. Evans, and L.J. Schulman, "On the maximum tolerable noise of k-input gates for reliable computations by formulas," IEEE Trans. Inform. Theory, vol. 49, Nov. 2003, pp. 3094-3098.
20. Y. Qi, J.B. Gao, and J.A.B. Fortes, "Markov chains and probabilistic computation - A general framework for multiplexed nanoelectronic systems," IEEE Trans. Nanotech., vol. 4, Mar. 2005, pp. 194-205.
21. J.B. Gao, Y. Qi, and J.A.B. Fortes, "Bifurcations and fundamental error bounds for fault-tolerant computations," IEEE Trans. Nanotech., vol. 4, Jul. 2005, pp. 395-402.
22. E.R. Taylor, J. Han, J.A.B. Fortes, "An investigation into the maximum tolerable error rate of majority gates for reliable computation," Intl. Worlshop on Defect and Fault Tolerant Nanoscale Arch. NANOARCH'06, Boston, MA, Jun. 2006, in press.
23. H. Iwamura, M. Akazawa, and Y. Amemiya, "Single-electron majority logic circuits," IEICE Trans. Electron., vol. E81-C, Jan. 1998, pp. 42-48.
24. C.P. Heij, P. Hadley, and J.E. Mooij, "Single-electron inverter," Appl. Phys. Lett., vol. 78, Feb. 2001, pp. 1140-1142.
25. Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara, and K. Murase, "Multigate single-electron transistors and their application to an Exclusive-OR gate," Appl. Phys. Lett., vol. 76, Jan. 2000, pp. 637-639.
26. J.R. Tucker, "Complementary digital logic based on the Coulomb blockade," J. Appl. Phys., vol. 72, Nov. 1992, pp. 4399-4413.
27. M. Sulieman, and V. Beiu, "Characterization of a 16-bit threshold logic single-electron technology adder," Proc. Intl. Symp. Circ. & Sys. ISCAS'04, Vancouver, Canada, May 2004, pp. 681-684.
28. M. Sulieman, and V. Beiu, "Design and analysis of SET circuits: Using MATLAB and SIMON," Proc. IEEE NANO'04, Munich, Germany, Aug. 2004, pp. 618-621.
29. C Wasshuber, H. Kosina, and S. Selberherr, "SIMON: A simulator for single-electron tunnel devices and circuits," IEEE Trans. Comp. Aided Design, vol. 16, Sep. 1997, pp. 937-944.
30. M. Kwiatkowska, G. Norman, and D. Parker, "PRISM: Probabilistic symbolic model checker," Proc. TOOLS'02, London, UK, Springer-Verlag LNCS vol. 2324, Apr. 2002, pp. 200-204 (see also www.cs.bham.ac.uk/~dxp/prism/) .
31. K.N. Patel, I.L. Markov, and J.P. Hayes, "Evaluating circuit reliability under probabilistic gate-level fault models," Proc. Intl. Workshop Logic Synthesis IWLS'03, Laguna Beach, CA, May 2003, pp. 59-64.
32. S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes, "Accurate reliability evaluation and enhancements via probabilistic transfer matrices," Proc. Design Autom. & Test in Europe DATE'05, Mar. 2005, pp. 282-287.
33. S. Krishnaswamy, I.L. Markov, and J.P. Hayes, "Logic circuit testing and transient faults," Proc. European Test Symp. ETS'05, Tallin, Estonia, May 2005, pp. 102-107.
34. J. Han, E.R. Taylor, J.B. Gao, and J.A.B. Fortes, "Faults, error bounds and reliability of nanoelectronic circuits," Proc. Intl. Conf. Appl.-Specific Sys., Arch. & Proc. ASAP'05, Jul. 2005, pp. 247-253.
35. S. Aunet, and V. Beiu, "Ultra low power fault tolerant neural inspired CMOS logic," Proc. Intl. Joint Conf. Neural Networks IJCNN'05, Montreal, Canada, Aug. 2005, pp. 2843-2848.