Ultra low power fault tolerant neural inspired CMOS logic

Proceedings of the International Joint Conference on Neural Networks

Volumn 5, Issue , 2005, Pages 2843-2848

  Aunet, Snorre ^a   Beiu, Valeriu ^b  

^a UNIVERSITY OF OSLO   (Norway)

^b Washington State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FAULT TOLERANT COMPUTER SYSTEMS; NEURAL NETWORKS; REDUNDANCY; THRESHOLD ELEMENTS; TRANSISTORS;

CHIP MEASUREMENTS; POWER-DELAY-PRODUCT; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 24944509428     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2005.1556376     Document Type: Conference Paper

References (30)

1. J. Rabaey, M. Pedram, P. Landman, in "Low Power Design Methodologies," Kluwer Academic Publishers , Boston, 1995.
2. E. J. Nowak "Maintaining the benefits of CMOS scaling when scaling bogs down," IBM J. Res. Dev. , pp. 169-180, Mar./May. 2002.
3. Leiv Eiriksson Nyskaping, Trondheim, Snorre Aunet "Norwegian patent application, no. 20035537," Dec. 2003.
4. S. Aunet, B. Oelmann, S. Abdalla, Y. Berg "Reconfigurable Subthreshold CMOS Perceptron," Int'l Joint Conf. Neural Networks, pp. 1983-1988, Jul. 2004.
5. V. Beiu, J. M. Quintana, and M. J. Avedillo, "VLSI Implementations of Threshold Logic - a Comprehensive Survey," IEEE Trans. Neural Networks, vol. 14, pp. 1217-1243, Sep. 2003.
6. J. B. Lerch, "Threshold Gate Circuits Employing Field-Effect Transistors" U. S. Patent 3 715 603, Feb. 6, 1973.
7. M. G. Johnson, "A Symmetric CMOS NOR Gate for High-Speed Applications ," IEEE J. Solid-State Circ., vol. 23, pp. 1233-1236, Oct. 1988.
8. K. J. Schultz, R. J. Francis, K. C. Smith, "Ganged CMOS: Trading Standby Power for Speed," IEEE J. Solid-State Oirc., vol. 25, pp. 870-873, Jun. 1990.
9. A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, E. J. Nowak; "Low Power CMOS at Vdd= 4kT/q", Proc. Device Research Conf. , pp. 22-23, Jun. 2001.
10. S. Aunet, M. Hartmann "Real Time reconfigurable Threshold Elements and Some Applications to Neural Hardware," Proc. Int'l Conf. Evaluable Systems: From Biology to Hardware , LNCS 2606, pp. 365-376, Norway, Mar. 17-20, 2003.
11. T. Kobayashi, T. Sakurai, "Self-adjusting Threshold-Voltage Scheme (SATS) for low-voltage high-speed operation," Proc. of the IEEE Custom Integrated Circuits Conf., San Diego, CA, USA, May 1994, pp. 271-274.
12. L. A. P. Melek, M. C. Schneider, C. Galup-Montoro; "Body Bias Compensation Technique for Subthreshold CMOS Static Logic Gates", Symp. Integrated Circuits Systems Design, pp. 7-11, Sep. 2004.
13. T. Shibata, T. Ohmi, "An intelligent MOS transistor featuring gate-level weighted sum and threshold operations," Technical Digest of Int'l Electron Devices Meeting, Washington DC, USA, Dec., 1991, pp. 919-922.
14. S. Aunet, Y. Berg, O. Tjore, Ø. Næss, T. Saether, "Four-MOSFET Floating-Gate UV-programmable Elements for Multifunction Binary Logic," Proc. World MultiConf. on Systemics, Cybernetics and Informatics , Orlando, FL, USA, Jul. 2001, vol. Ill, pp. 141-144.
15. T. Ytterdal, S. Aunet, "Compact Low-Voltage Self-Calibrating Digital Floating-Gate CMOS Logic Circuits," Proc. IEEE Int'l Symp. Circuits and Systems, Scottsdale, AZ, USA, vol. 5, pp. 393-396.
16. S. Aunet, T. Ytterdal, Y. Berg, T. Sæther, "Multiple-input Floating-Gate Linear Threshold Element Tuned by Well Potential Adjustment ," Proc. IEEE Norchip Conf. , Copenhagen, Denmark, Nov., 2002, pp. 220-225.
17. H. Iwamura, M. Akazawa, Y. Amemiya; "Single Electron Majority Logic Circuits" IEICE Trans. Electronics ,V E18 C, pp. 42-48, 1998.
18. S. Aunet, B. Oelmann, O. Lein, Y. Berg; "200 mV Full Adder Based on a Reconfigurable CMOS Perception", Proc. Int'l Conf. Circuits Electronic Systems , Sep. 2004.
19. S. Tatapudi, V. Beiu "Split-precharge differential noise immune threshold logic gate (SPD-DTL)," Proc. Int'l Work Conf. Artificial Neural Networks , Spain, LNCS 2687, pp. 49-56.
20. A. Schmid, Y. Leblebici "Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors," IEEE Conf. Nanotechn. , San Francisco, CA, USA, Aug. 2003, pp. 516-519.
21. A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasovic, R. E. Jenkins, K. Strohben, "Current-Mode Subthreshold MOS Circuits for Analog VLSI Neural Systems," IEEE Trans. Neural Networks, vol. 2, pp. 205-213, Mar. 1991.
22. B. H. Calhoun, A. Wang, A. Chandrakasan "Device Sizing for Minimum Energy Operation in Subthreshold Circuits," IEEE Custom Integrated Circuits Conf., pp. 95-98, Oct. 2004.
23. A. M. Shams, T. K. Darwish, M. A. Bayoumi; "Performance Analysis of Low Power 1 bit CMOS Full Adder Cells" IEEE Trans. Very Large Scale Integration (VLSI) Systems ,V 10, pp. 20-29, Feb. 2002.
24. S. Aunet, Y. Berg, T. Saether, "Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS," IEEE Trans. Neural Networks, vol. 14, pp. 1244-1256, Sep. 2003.
25. V. Beiu, S. Aunet, R. R. Rydberg III, A. Djupdal, J. Nyathi "The Vanishing Majority Gate: Trading Power and Speed for Reliability", accepted, final version to be submitted for IEEE Int'l Workshop Design and Test of Defect Tolerant Nanoscale Architectures , Palm Springs, CA, USA, May 2005.
26. V. Beiu, H. Makaruk, "Deeper Sparser Nets can be Optimal," Neural Proc. Letters , vol. 8, pp. 201-210, Dec. 1998.
27. J. T. Kao, M. Miyazaki, A. R. Chandrakasan; "A 175 mV Multiply Accumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture" IEEE J. Solid-State Circ., V 37, pp.. 1545-1554, Nov. 2002.
28. V. Beiu "A Novel Highly Reliable Nano Architecture when Von Neumann Augments Kolmogorov," IEEE Int'l Conf. Application Specific Systems Architectures and Processors, Galveston, Texas, USA pp. 167-177. Sep. 2004
29. Carver Mead; "Neuromorphic Electronic Systems" Proc. IEEE ,V 78, pp. 1629-1636, Oct. 1990.
30. K. K. Likharev "Neuromorphic CMOL circuits," IEEE Conf. Nanotechn. , vol. 2 San Francisco, USA pp. 339-342. Aug. 2003