Time-dependent dielectric breakdown characterization of 90- and 65-nm-Node Cu/SiOC interconnects with via plugs

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 46, Issue 4 A, 2007, Pages 1444-1451

  Ueno, Kazuyoshi ^a,b   Kameyama, Akiko ^a   Matsumoto, Akira ^a   Iguchi, Manabu ^a   Takewaki, Toshiyuki ^a   Oshida, Daisuke ^a   Toyoshima, Hironori ^a   Kawahara, Naoyoshi ^a   Asada, Susumu ^a   Suzuki, Mieko ^a   Oda, Noriaki ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Cu; Dielectric reliability; Interconnection; Low k; LSI; Time dependent dielectric breakdown

Indexed keywords

CHARACTERIZATION; ELECTRIC BREAKDOWN; ELECTRIC CONNECTORS; ELECTRIC FIELD EFFECTS; SILICA; THERMAL EFFECTS;

CHEMICAL-MECHANICAL POLISHING; E-MODEL; INTERMETAL DIELECTRICS; TDDB DEPENDENCES;

OPTICAL INTERCONNECTS;

EID: 34547865799     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.46.1444     Document Type: Article

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