Integration and reliability of Cu-SiOC interconnect for ArF/90-nm node CMOS technology

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2168-2174

  Noguchi, Junji ^a   Oshima, Takayuki ^a   Konishi, Nobuhiro ^a   Ishikawa, Kensuke ^a   Sato, Kiyohiko ^a   Uno, Syouichi ^a   Hotta, Syoji ^a   Saito, Tatsuyuki ^a   Aoki, Hideo ^a  

^a HITACHI LTD   (Japan)

Author keywords

Copper; Dielectric breakdown; Electromigration; Integrated circuit interconnections; Interface phenomena; Metallization; Permittivity; Reliability

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; DELAMINATION; ELECTRIC BREAKDOWN; ELECTROMIGRATION; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (MATERIALS); METALLIZING; PERMITTIVITY; RELIABILITY; SHORT CIRCUIT CURRENTS; SURFACE PHENOMENA;

DIELECTRIC BREAKDOWN; INTEGRATED CIRCUIT INTERCONNECTIONS; STRESS MIGRATION;

CMOS INTEGRATED CIRCUITS;

EID: 10644288644     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.839755     Document Type: Article

References (4)

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4. J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda, and K. Hinode, "TDDB improvement in Cu metallization under bias stress," in Proc. IRPS, 2000, pp. 339-343.