Transistor Sizing of Energy-Delay-Efficient Circuits

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Volumn , Issue , 2002, Pages 126-133

  Pénzes, Paul I ^a   Nyström, Mika ^a   Martin, Alain J ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Energy delay optimization; Transistor sizing

Indexed keywords

ALGORITHMS; ENERGY UTILIZATION; ITERATIVE METHODS; OPTIMIZATION; TRANSISTORS;

TRANSISTOR SIZING;

CMOS INTEGRATED CIRCUITS;

EID: 17944385563     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/589436.589439     Document Type: Conference Paper

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