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Volumn 3164, Issue , 2004, Pages 148-163

Coupled power and thermal simulation with active cooling

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COOLING; COOLING SYSTEMS; THERMAL MANAGEMENT (ELECTRONICS); POWER MANAGEMENT; VOLTAGE SCALING;

EID: 33947162957     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Article
Times cited : (13)

References (22)
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  • 6
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    • Wattch: A framework for architectural-level power analysis optimization
    • D.Brooks, V.Tiwari, and M.Martonosi, "Wattch: A framework for architectural-level power analysis optimization," in ISCA, 2000.
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    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 7
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    • Leakage power modeling and reduction with data retention
    • Nov
    • W. Liao, J. M. Basile, and L. He, "Leakage power modeling and reduction with data retention," in ICCAD 02, Nov 2002.
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    • Liao, W.1    Basile, J.M.2    He, L.3
  • 8
    • 2942747775 scopus 로고    scopus 로고
    • A static power model for architects
    • December
    • J. Butts and G. Sohi, "A static power model for architects," in Proc. of MICRO33, December 2000.
    • (2000) Proc. of MICRO33
    • Butts, J.1    Sohi, G.2
  • 9
    • 1542359151 scopus 로고    scopus 로고
    • Microarchitecture level power and thermal simulation considering temperature dependent leakage model
    • Aug
    • W. Liao, F. Li, and L. He, "Microarchitecture level power and thermal simulation considering temperature dependent leakage model," in ISLPED, Aug 2003.
    • (2003) ISLPED
    • Liao, W.1    Li, F.2    He, L.3
  • 12
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    • Aug.
    • S. Mutoh and et al, "1-v power supply high-speed digital circuit technology with multithreshold-voltage cmos," IEEE Journal of Solid-state circuits, vol. 30, pp. 847-854, Aug. 1995.
    • (1995) IEEE Journal of Solid-state Circuits , vol.30 , pp. 847-854
    • Mutoh, S.1
  • 14
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • P. Shivakumar and N. P. Jouppi, "Cacti 3.0: An integrated cache timing, power, and area model," in WRL Research Report 2001/2, 2001.
    • (2001) WRL Research Report 2001/2
    • Shivakumar, P.1    Jouppi, N.P.2
  • 15
    • 0031069405 scopus 로고    scopus 로고
    • A 600mhz superscalar rise microprocessor with out-of-order execution
    • B. A. Gieseke and et al, "A 600mhz superscalar rise microprocessor with out-of-order execution," in Proc. IEEE Int. Solid-State Circuits Conf., pp. 176-177, 1997.
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    • Gieseke, B.A.1
  • 16
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    • J. Stinson and S. Rusu, "A 1.5ghz third generation itanium 2 processor," in DAC, June 2003.
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  • 19
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    • Nov
    • R. Severns, "Safe operating area and thermal design for mospower transistors," in Siliconix applications note AN83-10, Nov 1983.
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  • 22
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    • Reducing power in high-performance microprocessors
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.