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Volumn 28, Issue 5, 2007, Pages 443-445

A high-performance body-tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-type flash memory

Author keywords

Bandgap engineered (BE) SONOS; Body tied FinFET; NAND flash; Nitride trapping memory

Indexed keywords

CHARGE TRAPPING; ENERGY GAP; FIELD EFFECT TRANSISTORS; NAND CIRCUITS; NITRIDES;

EID: 34247638062     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.895421     Document Type: Article
Times cited : (38)

References (16)
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    • Technology for sub-50 nm DRAM and NAND Flash Manufacturing
    • session 13-5
    • K. Kim, "Technology for sub-50 nm DRAM and NAND Flash Manufacturing," in IEDM Tech. Dig., 2005, pp. 323-326. session 13-5.
    • (2005) IEDM Tech. Dig , pp. 323-326
    • Kim, K.1
  • 6
    • 0038648963 scopus 로고    scopus 로고
    • Data retention, endurance and acceleration factors for NROM devices
    • M. Janai, "Data retention, endurance and acceleration factors for NROM devices," in Proc. IRPS, 2003, pp. 502-505.
    • (2003) Proc. IRPS , pp. 502-505
    • Janai, M.1
  • 8
    • 41149155436 scopus 로고    scopus 로고
    • S. K. Sung, S. H. Lee, B. Y. Choi, J. J. Lee, J. D. Choe, E. S. Cho, Y. J. Ahn, D. Choi, C. H. Lee, D. H. Kim, Y. S. Lee, S. B. Kim, D. Park, and B. Ryu, SONOS-type FinFET device using P+ Poly-Si gate and high-K blocking dielectric integrated on cell array and GSL/SSL for multi-Gigabit NAND memory, in VLSI Symp. Tech. Dig., Jun. 2006, pp. 86-87. PP.11.2.
    • S. K. Sung, S. H. Lee, B. Y. Choi, J. J. Lee, J. D. Choe, E. S. Cho, Y. J. Ahn, D. Choi, C. H. Lee, D. H. Kim, Y. S. Lee, S. B. Kim, D. Park, and B. Ryu, "SONOS-type FinFET device using P+ Poly-Si gate and high-K blocking dielectric integrated on cell array and GSL/SSL for multi-Gigabit NAND memory," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 86-87. PP.11.2.
  • 14
    • 23844527707 scopus 로고    scopus 로고
    • Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties
    • session 2D-3
    • H. T. Lue, Y. H. Shih, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties," in Proc. IRPS, 2005, pp. 168-174. session 2D-3.
    • (2005) Proc. IRPS , pp. 168-174
    • Lue, H.T.1    Shih, Y.H.2    Hsieh, K.Y.3    Liu, R.4    Lu, C.Y.5
  • 16
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    • A BE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory
    • session 1-4, to be published
    • H. T. Lue, S. Y Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A BE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory," in Proc. VLSI-TSA, 2007. session 1-4, to be published.
    • (2007) Proc. VLSI-TSA
    • Lue, H.T.1    Wang, S.Y.2    Lai, E.K.3    Hsieh, K.Y.4    Liu, R.5    Lu, C.Y.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.