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33847734692
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BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability
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H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," in IEDM Tech. Dig., 2005, pp. 547-550.
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Lue, H.T.1
Wang, S.Y.2
Lai, E.K.3
Shih, Y.H.4
Lai, S.C.5
Yang, L.W.6
Chen, K.C.7
Ku, J.8
Hsieh, K.Y.9
Liu, R.10
Lu, C.Y.11
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2
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21644480739
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8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology
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J. H. Park, S. H. Hur, J. H. Lee, J. T. Park, J. S. Sel, J. W. Kim, S. B. Song, J. Y. Lee, J. H. Lee, S. J. Son, Y. S. Kim, M. C. Park, S. J. Chai, J. D. Choi, U. I. Chung, J. T. Moon, K. T. Kim, K. Kim, and B. I. Ryu, "8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology," in IEDM Tech. Dig., 2004, pp. 873-876.
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Park, J.H.1
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Song, S.B.7
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Lee, J.H.9
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Chai, S.J.13
Choi, J.D.14
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Kim, K.18
Ryu, B.I.19
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3
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33847707730
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Technology for sub-50 nm DRAM and NAND Flash Manufacturing
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session 13-5
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K. Kim, "Technology for sub-50 nm DRAM and NAND Flash Manufacturing," in IEDM Tech. Dig., 2005, pp. 323-326. session 13-5.
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Kim, K.1
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FinFET scaling to 10 nm gate length
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B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, p. 251.
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Yu, B.1
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Ho, C.8
Xiang, Q.9
King, T.J.10
Bokor, J.11
Hu, C.12
Lin, M.R.13
Kyser, D.14
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5
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0141761522
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Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers
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T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in VLSI Symp. Tech. Dig., 2003, p. 135.
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Lee, C.G.7
Chi, K.K.8
Hong, S.H.9
Hyun, S.J.10
Shin, Y.G.11
Han, J.N.12
Park, I.S.13
Chung, U.I.14
Moon, J.T.15
Yoon, E.16
Lee, J.H.17
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6
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Data retention, endurance and acceleration factors for NROM devices
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M. Janai, "Data retention, endurance and acceleration factors for NROM devices," in Proc. IRPS, 2003, pp. 502-505.
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Proc. IRPS
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Janai, M.1
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7
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33847766179
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20 nm gate bulk-FinFET SONOS flash
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Dec
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J. R. Hwang, T. L. Lin, H. C. Ma, T. C. Lee, T. H. Chung, C. Y. Chang, S. D. Liu, B. C. Perng, J. W. Hsu, M. Y. Lee, C. Y. Ting, C. C. Huang, J. H. Wang, J. H. Shieh, and F. L. Yang, "20 nm gate bulk-FinFET SONOS flash," in IEDM Tech. Dig., Dec. 2005, pp. 154-157.
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Hwang, J.R.1
Lin, T.L.2
Ma, H.C.3
Lee, T.C.4
Chung, T.H.5
Chang, C.Y.6
Liu, S.D.7
Perng, B.C.8
Hsu, J.W.9
Lee, M.Y.10
Ting, C.Y.11
Huang, C.C.12
Wang, J.H.13
Shieh, J.H.14
Yang, F.L.15
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S. K. Sung, S. H. Lee, B. Y. Choi, J. J. Lee, J. D. Choe, E. S. Cho, Y. J. Ahn, D. Choi, C. H. Lee, D. H. Kim, Y. S. Lee, S. B. Kim, D. Park, and B. Ryu, SONOS-type FinFET device using P+ Poly-Si gate and high-K blocking dielectric integrated on cell array and GSL/SSL for multi-Gigabit NAND memory, in VLSI Symp. Tech. Dig., Jun. 2006, pp. 86-87. PP.11.2.
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S. K. Sung, S. H. Lee, B. Y. Choi, J. J. Lee, J. D. Choe, E. S. Cho, Y. J. Ahn, D. Choi, C. H. Lee, D. H. Kim, Y. S. Lee, S. B. Kim, D. Park, and B. Ryu, "SONOS-type FinFET device using P+ Poly-Si gate and high-K blocking dielectric integrated on cell array and GSL/SSL for multi-Gigabit NAND memory," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 86-87. PP.11.2.
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Erase characteristics of p-channel bulk FinFET SONOS flash memory
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I. H. Cho, T.-S. Park, D. G. Park, H. Shin, B.-G. Park, J. D. Lee, and J.-H. Lee, "Erase characteristics of p-channel bulk FinFET SONOS flash memory," in Proc. IEEE Silicon Nanoworkshop, 2005, pp. 40-41.
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Proc. IEEE Silicon Nanoworkshop
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Cho, I.H.1
Park, T.-S.2
Park, D.G.3
Shin, H.4
Park, B.-G.5
Lee, J.D.6
Lee, J.-H.7
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10
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34247576814
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Fully integrated SONOS flash memory cell array with BT-FinFET structure
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S. K. Sung, T. Y. Kim, E. S. Cho, H. J. Cho, B. Y. Choi, C. W. Oh, B. G. Cho, C. H. Lee, and D. Park, "Fully integrated SONOS flash memory cell array with BT-FinFET structure," in Proc. IEEE Silicon Nanoworkshop 2005, pp. 102-103.
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Sung, S.K.1
Kim, T.Y.2
Cho, E.S.3
Cho, H.J.4
Choi, B.Y.5
Oh, C.W.6
Cho, B.G.7
Lee, C.H.8
Park, D.9
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11
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4544344826
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Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications
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Jun
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M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgtaf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch, "Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 244-245.
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Alvarez, D.6
Kretz, J.7
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Rosner, W.9
Reisinger, H.10
Landgtaf, E.11
Schulz, T.12
Hartwich, J.13
Stadele, M.14
Klandievski, V.15
Hartmann, E.16
Risch, L.17
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12
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20 nm tri-gate SONOS memory cells with multi-level operation
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Dec
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M. Specht, U. Dorda, L. Dreeskornfeld, J. Kretz, F. Hofmann, M. Stadele, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgtaf, T. Schulz, J. Hartwich, R. Kommling, and L. Risch, "20 nm tri-gate SONOS memory cells with multi-level operation," in IEDM Tech. Dig., Dec. 2004, pp. 1083-1087.
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Specht, M.1
Dorda, U.2
Dreeskornfeld, L.3
Kretz, J.4
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Stadele, M.6
Luyken, R.J.7
Rosner, W.8
Reisinger, H.9
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Schulz, T.11
Hartwich, J.12
Kommling, R.13
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13
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On the go with SONOS
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Jul
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M. H. White, D. A. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, Jul. 2000.
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14
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23844527707
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Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties
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session 2D-3
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H. T. Lue, Y. H. Shih, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties," in Proc. IRPS, 2005, pp. 168-174. session 2D-3.
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Proc. IRPS
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Lue, H.T.1
Shih, Y.H.2
Hsieh, K.Y.3
Liu, R.4
Lu, C.Y.5
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15
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46049090436
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Reliability model of bandgap engineered SONOS (BE-SONOS)
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H. T. Lue, S. Y. Wang, Y. H. Hsiao, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Reliability model of bandgap engineered SONOS (BE-SONOS)," in IEDM Tech. Dig., 2006, pp. 495-498.
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Lue, H.T.1
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Chen, K.C.7
Hsieh, K.Y.8
Liu, R.9
Lu, C.Y.10
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16
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34548844731
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A BE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory
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session 1-4, to be published
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H. T. Lue, S. Y Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A BE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era flash memory," in Proc. VLSI-TSA, 2007. session 1-4, to be published.
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(2007)
Proc. VLSI-TSA
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Lue, H.T.1
Wang, S.Y.2
Lai, E.K.3
Hsieh, K.Y.4
Liu, R.5
Lu, C.Y.6
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