Data retention, endurance and acceleration factors of NROM devices

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 502-505

  Janai, Meir ^a  

^a Saifun Semiconductors Ltd   (Israel)

Author keywords

Acceleration Factor; Endurance; NROM; NVM; Product Reliability; Qualification; Retention; Trapped charge

Indexed keywords

ACCELERATION; CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS;

DATA RETENTION;

ROM;

EID: 0038648963     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi. "Can NROM, a 2-bit trapping storage cell, give a real challenge to floating gate cells?" in Proc. SSDM 1999, Tokyo, Japan, pp. 522-524, Sept. 1999; P. Clarke, "AMD, Fujitsu, Saifun to team up on multi-bit flash," in EE Times, July 30, 2002;
2. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi. "Can NROM, a 2-bit trapping storage cell, give a real challenge to floating gate cells?" in Proc. SSDM 1999, Tokyo, Japan, pp. 522-524, Sept. 1999; P. Clarke, "AMD, Fujitsu, Saifun to team up on multi-bit flash," in EE Times, July 30, 2002;
3. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, D. Finzi, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", in IEEE Electron Device Lett., vol. 21 pp. 543-545, Nov. 2000
4. P. Pavan, R. Bez, P. Olivio, E. Zanoni, "Flesh Memory Cells an Overview, in Proc. Of the IEEE, Vol.85, No.8 pp. 1248-1271, 1997
5. E. Lusky, Y. Shacham-Diamand, I. Bloom and B. Eitan, "Electron Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric", in IEEE Electron Device Lett., vol. 23, pp 556-558 Sep. 2002.
6. JEDEC STANDARD JESD22-A103-B "High Temperature Storage Life", JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, Aug. 2001
7. JEDEC STANDARD JESD22-A117, "Electrically Erasable Programmable ROM Program/Erase Endurance and Data Retention Test", JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, Jan. 2000