SONOS-type FinFET device using P+ poly-Si gate and high-k blocking dielectric integrated on cell array and GSL/SSL for multi-gigabit NAND flash memory

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 86-87

  Sung, Suk Kang ^a   Lee, Se Hoon ^a   Choi, Byung Yong ^a   Lee, Jong Jin ^a   Choe, Jeong Dong ^a   Cho, Eun Suk ^a   Ahn, Young Joon ^a   Choi, Donguk ^a   Lee, Choong Ho ^a   Kim, Dong Hyun ^a   Lee, Yong Seok ^a   Kim, Seung Beom ^a   Park, Donggun ^a   Ryu, Byung Il ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; NAND CIRCUITS; PERMITTIVITY;

CELL ARRAYS; FINFET DEVICES;

FLASH MEMORY;

EID: 41149155436     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. J. -D. Lee, et al., IEEEEDL., p.748, 2003.
2. J. -D. Lee, et al., IEEE EDL., p.264, 2002.
3. B. Yu, et al., IEDM.Tech. Dig., p.251, 2002.
4. T. Park, et al., VLSI Symp. Tech. Dig., p.135, 2003.
5. C. H. Lee, et al., IEDM.Tech. Dig., p.613, 2003.
6. S. Jeon, et al., IEEE TED., p.2654, 2005.
7. K. Yanagidaira, et al., Jpn. J. Appl. Phys.. p.2608, 2005.
8. J. J. Lee, et al., IRPS, 2005, to be published.
9. L. Chang, et al., IEDM.Tech. Dig., p.99, 2001.