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Volumn 2005, Issue , 2005, Pages 154-157

20nm gate bulk-FinFET SONOS flash

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); SILICA;

EID: 33847766179     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (34)

References (13)
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    • Yang, F.L.1
  • 3
    • 0037646045 scopus 로고    scopus 로고
    • Advanced depleted-substrate transistors: Single-gate, double-gate and tri-gate
    • Nogoya, pp, September
    • R. Chau et al., "Advanced depleted-substrate transistors: single-gate, double-gate and tri-gate," in International Conference on Solid State Devices and Materials, Nogoya, pp. 68-69, September 2002.
    • (2002) International Conference on Solid State Devices and Materials , pp. 68-69
    • Chau, R.1
  • 4
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    • PMOS body-tied FinFET (Omega MOSFET) characteristics
    • June
    • T. Park et al., "PMOS body-tied FinFET (Omega MOSFET) characteristics," in 2003 Device Research Conference, pp. 33-34, June 2003.
    • (2003) 2003 Device Research Conference , pp. 33-34
    • Park, T.1
  • 5
    • 0026107524 scopus 로고
    • ONO inter-poly dielectric scaling for nonvolatile memory applications
    • February
    • S. Mori et al., "ONO inter-poly dielectric scaling for nonvolatile memory applications," in IEEE Transactions on Electron Devices, vol. 38, pp. 386-391, February 1991.
    • (1991) IEEE Transactions on Electron Devices , vol.38 , pp. 386-391
    • Mori, S.1
  • 6
    • 17644429462 scopus 로고    scopus 로고
    • A 6V embedded 90nm silicon nanocrystal non-volatile memory
    • December
    • R. Muralidhar et al., "A 6V embedded 90nm silicon nanocrystal non-volatile memory," in IEDM Tech. Dig., pp. 601-604, December 2003.
    • (2003) IEDM Tech. Dig , pp. 601-604
    • Muralidhar, R.1
  • 7
    • 0842266589 scopus 로고    scopus 로고
    • High speed and non-volatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier
    • December
    • S. J. Baik, S. Choi, U. Chung, and J. T. Moon, "High speed and non-volatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier," in IEDM Tech. Dig., pp. 545-548, December 2003.
    • (2003) IEDM Tech. Dig , pp. 545-548
    • Baik, S.J.1    Choi, S.2    Chung, U.3    Moon, J.T.4
  • 9
    • 33646720123 scopus 로고    scopus 로고
    • Body-tied double-gate SONOS flash (Omega flash) memory device built on bulk Si wafer
    • June
    • I. H. Cho, T.-S. Park, S. Y. Choi, J. D. Lee, and J.-H. Lee, "Body-tied double-gate SONOS flash (Omega flash) memory device built on bulk Si wafer," in 2003 Device Research Conference, pp. 133-134, June 2003.
    • (2003) 2003 Device Research Conference , pp. 133-134
    • Cho, I.H.1    Park, T.-S.2    Choi, S.Y.3    Lee, J.D.4    Lee, J.-H.5
  • 10
    • 4544344826 scopus 로고    scopus 로고
    • Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications
    • June
    • M. Specht et al., "Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications," in 2004 Symposium on VLSI Tech. Dig., pp. 244-245, June 2004.
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    • Specht, M.1
  • 11
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    • 20nm tri-gate SONOS memory cells with multi-level operation
    • December
    • M. Specht et al., "20nm tri-gate SONOS memory cells with multi-level operation," in IEDM Tech. Dig., pp. 1083-1087, December 2004.
    • (2004) IEDM Tech. Dig , pp. 1083-1087
    • Specht, M.1
  • 12
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    • Ultrashort SONOS memories
    • December
    • M. K. Kim et al., "Ultrashort SONOS memories," in IEEE Transactions on Nanotechnology, vol. 3, pp. 417-424, December 2004.
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  • 13
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    • Secondary electron flash - a high performance, low power flash technology for 0.35μm and below
    • December
    • J. D. Bude et al., "Secondary electron flash - a high performance, low power flash technology for 0.35μm and below," in IEDM Tech. Dig., pp. 279-282, December 1997.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.