A two-dimensional model for interface coupling in triple-gate transistors

IEEE Transactions on Electron Devices

Volumn 54, Issue 4, 2007, Pages 767-775

  Akarvardar, Kerem ^a,b   Mercha, Abdelkarim ^c   Cristoloveanu, Sorin ^a   Gentil, Pierre ^a,d   Simoen, Eddy ^c   Subramanian, Vaidy ^c   Claeys, Cor ^c,e  

^a IMEP LAHC   (France)

^b Stanford University   (United States)

^c IMEC   (Belgium)

^d Grenoble INP Phelma   (France)

^e UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Coupling effects; Fin field effect transistor (FinFET); Fin width extraction; Fringing fields; Multiple gate transistor; Silicon on insulator (SOI); Threshold voltage; Triple gate transistor; Two dimensional (2 D) modeling; Undoped body

Indexed keywords

BIAS VOLTAGE; COUPLED CIRCUITS; MATHEMATICAL MODELS; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THRESHOLD VOLTAGE; TWO DIMENSIONAL;

FIN WIDTH EXTRACTION; INTERFACE COUPLING; MULTIPLE-GATE TRANSISTOR; TRIPLE-GATE TRANSISTOR;

GATES (TRANSISTOR);

EID: 34147169315     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.892364     Document Type: Article

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