Lateral coupling and immunity to substrate effect in ΩFET devices

Solid-State Electronics

Volumn 50, Issue 4, 2006, Pages 558-565

  Ritzenthaler, R ^a   Cristoloveanu, S ^a,b   Faynot, O ^a   Jahan, C ^a   Kuriyama, A ^a   Brevard, L ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

^b IMEP LAHC   (France)

Author keywords

FET; Back gate biasing; Coupling effects; Drain induced virtual substrate biasing (DIVSB); FinFET; Lateral coupling; SOI

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; NUMERICAL ANALYSIS; THREE DIMENSIONAL;

BACK-GATE BIASING; COUPLING EFFECTS; DRAIN-INDUCED VIRTUAL SUBSTRATE BIASING (DIVSB); FINFET; LATERAL COUPLINGS; SOI;

FIELD EFFECT TRANSISTORS;

EID: 33646519429     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.03.025     Document Type: Article

References (11)

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