Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

IEEE Transactions on Electron Devices

Volumn 53, Issue 10, 2006, Pages 2569-2577

  Akarvardar, Kerem ^a   Cristoloveanu, Sorin ^a   Gentil, Pierre ^a  

^a MINATEC   (France)

Author keywords

Charge sharing; Drain induced barrier lowering; Four gate transistor; Junction FET (JFET); MOSFET; Multiple gate transistor; Potential distribution; Short channel effect; Silicon on insulator (SOI); Threshold voltage; Two dimensional (2 D) modeling

Indexed keywords

CHARGE SHARING; DRAIN-INDUCED BARRIER LOWERING; FOUR-GATE TRANSISTOR; JUNCTION FET (JFET); MOSFET; MULTIPLE-GATE TRANSISTOR; POTENTIAL DISTRIBUTION; SHORT-CHANNEL EFFECT; SILICON-ON-INSULATOR (SOI); TWO-DIMENSIONAL (2-D) MODELING;

ELECTROMAGNETIC INDUCTION; FIELD EFFECT TRANSISTORS; MESFET DEVICES; MICROSENSORS; POISSON EQUATION; SEMICONDUCTING SILICON COMPOUNDS; THRESHOLD VOLTAGE; TWO DIMENSIONAL;

MOSFET DEVICES;

EID: 34147100882     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.882283     Document Type: Article

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