Threshold voltage model of the SOI 4-gate transistor

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 89-90

  Akarvardar, K ^a   Cristoloveanu, S ^a   Gentil, P ^a  

^a IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; MATHEMATICAL MODELS; MOS DEVICES; POISSON EQUATION; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

CHARGE COUPLING; DRAIN VOLTAGE; GATE VOLTAGES; MOS GATES;

GATES (TRANSISTOR);

EID: 16244388560     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B.J. Blalock, S. Cristoloveanu, B. M. Dufrene, F. Allibert and M. Mojarradi, Int. Journal of High Speed Electronics and Systems, 12(2), pp. 511-520, 2002.
2. H.-K. Lim and J. G. Fossum IEEE Trans. on Electron Devices, 30(10), pp. 1244-1251, 1983.
3. K. K. Young, IEEE Trans. on Electron Devices, 36(2), pp. 399-402, 1989.
4. K. Akarvardar, B. Dufrene, S. Cristoloveanu, B. J. Blalock, T. Higashino, M. M. Mojarradi, and E. Kolawa, in Proc. ESSDERC, pp. 127-130, 2003.