Design methodology for global resonant H-tree clock distribution networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 2, 2007, Pages 135-148

  Rosenfeld, Jonathan ^b   Friedman, Eby G ^a,b  

^a IEEE

^b University of Rochester   (United States)

Author keywords

H tree sector; On chip inductors and capacitors; Resonant clock distribution networks; Sensitivity

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC LINES; ELECTRIC POWER DISTRIBUTION; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; TIMING JITTER;

H-TREE SECTOR; ON-CHIP CAPACITORS; ON-CHIP INDUCTORS; RESONANT CLOCK DISTRIBUTION NETWORKS;

LOGIC CIRCUITS;

EID: 34047097349     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893576     Document Type: Article

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