-
1
-
-
0035334849
-
A clock distribution network for microprocessors
-
May
-
P. J. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-799, May 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 792-799
-
-
Restle, P.J.1
-
2
-
-
0028436854
-
Salphasic distribution of clock signals for synchronous systems
-
May
-
V. L. Chi, "Salphasic distribution of clock signals for synchronous systems," IEEE Trans. Comput., vol. 43, pp. 597-602, May 1994.
-
(1994)
IEEE Trans. Comput.
, vol.43
, pp. 597-602
-
-
Chi, V.L.1
-
4
-
-
0029322459
-
Operation of a 1-bit quantum flux parametron shift register (latch) by 4-phase 36-GHz clock
-
June
-
M. Hosoya, W. Hioe, K. Takagi, and E. Goto, "Operation of a 1-bit quantum flux parametron shift register (latch) by 4-phase 36-GHz clock," IEEE Trans. Appl. Superconduct., vol. 5, pp. 2831-2834, June 1995.
-
(1995)
IEEE Trans. Appl. Superconduct.
, vol.5
, pp. 2831-2834
-
-
Hosoya, M.1
Hioe, W.2
Takagi, K.3
Goto, E.4
-
5
-
-
0035507075
-
Rotary travelling-wave oscillator arrays: A new clock technology
-
Nov.
-
J. Wood, T. C. Edwards, and S. Lipa, "Rotary travelling-wave oscillator arrays: a new clock technology," IEEE J. Solid-State Circuits, vol. 36, pp. 1654-1665, Nov. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1654-1665
-
-
Wood, J.1
Edwards, T.C.2
Lipa, S.3
-
6
-
-
0029716091
-
Clock distribution using coupled oscillators
-
May
-
I. Galton, D. A. Towne, J. J. Rosenberg, and H. T. Jensen, "Clock distribution using coupled oscillators," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, May 1996, pp. 217-220.
-
(1996)
Proc. IEEE Int. Symp. Circuits and Systems
, vol.3
, pp. 217-220
-
-
Galton, I.1
Towne, D.A.2
Rosenberg, J.J.3
Jensen, H.T.4
-
7
-
-
0031343682
-
Clock distribution using cooperative ring oscillators
-
L. Hall, M. Clements, W. Liu, and G. Bilbro, "Clock distribution using cooperative ring oscillators," in Proc. 17th Conf. Advanced Research in VLSI, Sept. 1997, pp. 15-16.
-
Proc. 17th Conf. Advanced Research in VLSI, Sept. 1997
, pp. 15-16
-
-
Hall, L.1
Clements, M.2
Liu, W.3
Bilbro, G.4
-
8
-
-
0034316214
-
Active GHz clock network using distributed PLLs
-
Nov.
-
V. Gutnik and A. P. Chandrakasan, "Active GHz clock network using distributed PLLs," IEEE J. Solid-State Circuits, vol. 35, pp. 1553-1560, Nov. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1553-1560
-
-
Gutnik, V.1
Chandrakasan, A.P.2
-
9
-
-
0035183671
-
On the micro-architectural impact of clock distribution using multiple PLLs
-
M. Saint-Laurent, M. Swaminathoan, and J. D. Meindl, "On the micro-architectural impact of clock distribution using multiple PLLs," in Proc. IEEE Int. Conf. Computer Design, Sept. 2001, pp. 214-220.
-
Proc. IEEE Int. Conf. Computer Design, Sept. 2001
, pp. 214-220
-
-
Saint-Laurent, M.1
Swaminathoan, M.2
Meindl, J.D.3
-
10
-
-
0026943895
-
Active compensation of interconnect losses for multi-GHz clock distribution networks
-
Nov.
-
M. Bussmann and U. Langmann, "Active compensation of interconnect losses for multi-GHz clock distribution networks," IEEE Trans. Circuits Syst. II, vol. 39, pp. 790-798, Nov. 1992.
-
(1992)
IEEE Trans. Circuits Syst. II
, vol.39
, pp. 790-798
-
-
Bussmann, M.1
Langmann, U.2
-
11
-
-
0024737887
-
Attenuation compensation in distributed amplifier design
-
Sept.
-
S. Deibele and J. B. Beyer, "Attenuation compensation in distributed amplifier design," IEEE Trans. Microwave Theory Tech., vol. MTT-37, pp. 1425-1433, Sept. 1989.
-
(1989)
IEEE Trans. Microwave Theory Tech.
, vol.MTT-37
, pp. 1425-1433
-
-
Deibele, S.1
Beyer, J.B.2
-
12
-
-
0027684375
-
Nonlinear analysis of phase relationships in quasi-optical oscillator arrays
-
Oct.
-
R. A. York, "Nonlinear analysis of phase relationships in quasi-optical oscillator arrays," IEEE Trans. Microwave Theory Tech., vol. 41, pp. 1799-1809, Oct. 1993.
-
(1993)
IEEE Trans. Microwave Theory Tech.
, vol.41
, pp. 1799-1809
-
-
York, R.A.1
-
13
-
-
0035506811
-
A low jitter 125-1250 MHz process independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter
-
Nov.
-
A. Maxim, B. Scott, E. M. Schneider, M. L. Hagge, S. Chacko, and D. Stiurca, "A low jitter 125-1250 MHz process independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter," IEEE J. Solid-State Circuits, vol. 36, pp. 1673-1683, Nov. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1673-1683
-
-
Maxim, A.1
Scott, B.2
Schneider, E.M.3
Hagge, M.L.4
Chacko, S.5
Stiurca, D.6
-
14
-
-
0042630246
-
The nonlinear theory of electric oscillations
-
Sept.
-
B. Van der Pol, "The nonlinear theory of electric oscillations," Proc. IRE, vol. 22, pp. 1051-1085, Sept. 1934.
-
(1934)
Proc. IRE
, vol.22
, pp. 1051-1085
-
-
Van Der Pol, B.1
|