Uniform-phase uniform-amplitude resonant-load global clock distributions

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 102-109

  Chan, Steven C ^a   Shepard, Kenneth L ^a   Restle, Phillip J ^b  

^a Department of Earth and Environmental Sciences   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Clock distribution; Inductance; Jitter; Resonant clocking; Skew; Timing circuits

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC FIELD EFFECTS; ELECTRIC POWER UTILIZATION; JITTER; MAGNETIC FIELD EFFECTS; NATURAL FREQUENCIES; RESONANCE; TIMING CIRCUITS;

CLOCK DISTRIBUTION; RESONANT CLOCKING; SKEW;

ELECTRIC INDUCTORS;

EID: 11944274850     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.838005     Document Type: Conference Paper

References (16)

1. P. J. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 792-799, May 2001.
2. N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, "A multigigahertz clocking scheme for the Pentium 4 microprocessor," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1647-1653, Nov. 2001.
3. M. I. Pupin, "Electrical Transmission by Resonance Circuits," U.S. Patent no. 640516, 1900.
4. V. L. Chi, "Salphasic distribution of clock signals for synchronous systems," IEEE Trans. Comput., vol. 43, no. 5, pp. 597-602, May 1994.
5. J. Wood, T. C. Edwards, and S. Lipa, "Rotary traveling-wave oscillator arrays: A new clock technology," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1654-1665, Nov. 2001.
6. F. O'Mahony, C. P. Yue, M. A. Horowitz, and S. S. Wong, "A 10-GHz global clock distribution using coupled standing-wave oscillators," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1813-1820, Nov. 2003.
7. B. Kleveland et al., "Monolithic CMOS distributed amplifier and oscillator," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 36, Feb. 1999, pp. 70-71.
8. H. Wu and A. Hajimiri, "Silicon-based distributed voltage-controlled oscillators," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 493-502, Mar. 2001.
9. W. C. Athas, L. J. Svensson, and N. Tzartanis, "A resonant signal driver for two-phase, almost-nonoverlapping clocks," in Int. Symp. Circuits Syst., 1996, pp. 129-132.
10. T. Ye and K. Roy, "QSERL: Quasistatic energy recovery logic," IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 239-248, Feb. 2001.
11. A. J. Drake, K. J. Nowka, T. Y. Nguyen, J. L. Burns, and R. B. Brown, "Resonant clocking using distributed parasitic capacitance," in Proc. Int. Custom Integrated Circuits Conf., 2003, pp. 647-650.
12. S. C. Chan, P. J. Restle, K. L. Shepard, N. K. James, and R. L. Franch, "A 4.6 GHz resonant global clock distribution network," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 342-343.
13. S. C. Chan, K. L. Shepard, and P. J. Restle, "Design of resonant global clock distributions," in Proc. Int. Conf. Comput. Design, 2003, pp. 238-243.
14. P. J. Restle, A. E. Ruehli, S. G. Walker, and G. Papadopoulos, "Full-wave PEEC time-domain method for the modeling of on-chip interconnects," IEEE Trans. Computer Aided Design, vol. 20, no. 7, pp. 877-887, Jul. 2001.
15. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF IC's," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.
16. A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, "On-die droop detector for analog sensing of power supply noise," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 651-660, Apr. 2004.