Impact of interconnect process variations on memory performance and design

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 694-699

  Teene, A ^a   Davis, B ^a   Castagnetti, R ^a   Brown, J ^a   Ramesh, S ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE MODELING; INTERCONNECT PARASITICS; MEMORY PERFORMANCE; PARASITIC EXTRACTION; PERFORMANCE SENSITIVITY; PROCESS PARAMETER VARIATIONS; PROCESS VARIATION; STATISTICAL DESIGN;

HETEROJUNCTION BIPOLAR TRANSISTORS; INTERCONNECTION NETWORKS; SENSITIVITY ANALYSIS;

DESIGN;

EID: 84886644176     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.63     Document Type: Conference Paper

References (12)

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