Timing analysis taking into account interconnect process variation

International Workshop on Statistical Metrology, Proceedings, IWSM

Volumn , Issue , 2001, Pages 51-53

  Dai, W ^a   Ji, H ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; CRITICAL PATH ANALYSIS; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; MONTE CARLO METHODS; TIMING CIRCUITS; VLSI CIRCUITS;

SYSTEM-ON-CHIP DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034779058     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Statistical metrology: Understanding spatial variation in semiconductor manufacturing
2. Statistical metrology - Measurement and modeling of variation for advanced process development and design rule generation
3. Within-chip variability analysis
4. Design for variability in DSM technologies