Fully-depleted FBC (Floating Body Cell) with enlarged signal window and excellent logic process compatibility

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 281-282

  Shino, Tomoaki ^a   Higashi, Tomoki ^a   Kusunoki, Naoki ^a   Fujita, Katsuyuki ^a   Ohsawa, Takashi ^a   Aoki, Nobutoshi ^a   Tanimoto, Hiroyoshi ^a   Minami, Yoshihiro ^a   Yamada, Takashi ^a   Morikado, Mutsuo ^a   Nakajima, Hiroomi ^a   Inoh, Kazumi ^a   Hamamoto, Takeshi ^a   Nitayama, Akihiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC FIELDS; EMBEDDED SYSTEMS; IMPACT IONIZATION; LOGIC CIRCUITS; MODULATION; SUBSTRATES; THRESHOLD VOLTAGE; FINITE DIFFERENCE METHOD; SILICON ON INSULATOR TECHNOLOGY;

BITLINES; DATA STATES; HIGH-SPEED WRITING; PLATE BIAS;

SILICON ON INSULATOR TECHNOLOGY; COMPUTER CIRCUITS;

EMBEDDED MEMORY; FLOATING-BODY CELL; FULLY DEPLETED; LOGIC PROCESS; NEGATIVE SUBSTRATES; PROCESS COMPATIBILITY; SALICIDES; SUBSTRATE BIAS;

EID: 18144376522     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. K.Inoh, et al., "FBC (Floating Body Cell) for Embedded DRAM on SOI", 2003 Symp. on VLSI Technology, pp.63.
2. Shino, et al., "Highly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications", 2004 Symp. on VLSI Technology, pp.132.