An 18.5ns 128Mb SOI DRAM with a floating body cell

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Ohsawa, Takashi ^a   Fujita, Katsuyuki ^a   Hatsuda, Kosuke ^a   Higashi, Tomoki ^a   Morikado, Mutsuo ^a   Minami, Yoshihiro ^a   Shino, Tomoaki ^a   Nakajima, Hiroomi ^a   Inoh, Kazumi ^a   Hamamoto, Takeshi ^a   Watanabe, Shigeyoshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144449075     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. Okhonin et al., "SOI Capacitor-Less IT-DRAM Concept," IEEE Int. SOI Conference, pp. 153-154, Oct., 2001.
2. T. Ohsawa et al., "Memory Design using One-Transistor Gain Cell on SOI," ISSCC Dig. Tech. Papers, pp.152-153, Feb., 2002.
3. R. Ranica et al., "A One Transistor Cell on Bulk Substrate(1T-Bulk) for Low-Cost and High Density eDRAM," Symp. VLSI Technology, pp.128-129, June, 2004.
4. T. Ohsawa et al., "A Memory using One-Transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's," Symp. VLSI Circuits, pp.93-96, June, 2003.
5. S. Okhonin et al., "Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs," IEEE Electron Device Lett., vol.23, no.5, pp.279-281, May, 2002.
6. K. Sawada et al., "A 30-μA Data-Retention Pseudostatic RAM with Virtually Static RAM Mode," IEEE J. Solid-State Circuits, vol.23, no.1, pp.12-19, Feb., 1988.