A high performance 100 nm generation SOC technology [CMOS IV] for high density embedded memory and mixed signal LSIs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 11-12

  Miyashita, K ^a   Nakayama, T ^a   Oishi, A ^a   Hasumi, R ^a   Owada, M ^a   Aota, S ^a   Okayama, Y ^a   Matsumoto, M ^a   Igarashi, H ^a   Yoshida, T ^a   Kasai, K ^a   Yoshitomi, T ^a   Fukaura, Y ^a   Kawasaki, H ^a   Ishimaru, K ^a   Adachi, K ^a   Fujiwara, M ^a   Ohuchi, K ^a   Takayanagi, M ^a   Oyamatsu, H ^a   Matsuoka, F ^a   Noguchi, T ^a   Kakumu, M ^a   more..

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CHIP SCALE PACKAGES; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); LSI CIRCUITS; MIM DEVICES; STATIC RANDOM ACCESS STORAGE;

EMBEDDED MEMORY; SYSTEM ON CHIP (SOC) TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 0034796390     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)