A capacitor-less DRAM cell on 75nm gate length, 16nm thin Fully Depleted SOI device for high density embedded memories

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 277-280

  Ranica, R ^a   Villaret, A ^a   Fenouillet Beranger, C ^c   Malinge, P ^a   Mazoyer, P ^a   Masson, P ^d   Delille, D ^b   Charbuillet, C ^a   Candelier, P ^a   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

^c CEA LETI   (France)

^d AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EMBEDDED SYSTEMS; LITHOGRAPHY; MODULATION; OXIDATION; PERTURBATION TECHNIQUES; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS; FINITE DIFFERENCE METHOD;

CROSS-SECTIONS; DRAIN VOLTAGE; NEGATIVE BIAS; RETENTION TIME;

DYNAMIC RANDOM ACCESS STORAGE;

CAPACITOR-LESS; DRAM CELLS; EMBEDDED MEMORY; FULLY DEPLETED DEVICES; FULLY DEPLETED SOI; GATE-LENGTH; MEMORY OPERATIONS; OPERATION MECHANISM; SOI DEVICES; VERY THIN FILMS;

EID: 21644483754     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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