Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 11, 2005, Pages 1286-1295

  Chen, Qikai ^a,b   Mahmoodi, Hamid ^a,c   Bhunia, Swarup ^a,b   Roy, Kaushik ^a,b  

^a IEEE   (United States)

^b PURDUE UNIVERSITY   (United States)

^c SAN FRANCISCO STATE UNIVERSITY   (United States)

Author keywords

Design for test (DFT); Failure mechanism; March test; Process variation; SRAM

Indexed keywords

FAILURE MECHANISM; LOGIC FAULT MODELS; MARCH TESTS; PROCESS VARIATION;

CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; ELECTRIC FAULT CURRENTS; LOGIC DEVICES; SEMICONDUCTOR DEVICE TESTING; TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 33947143498     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859565     Document Type: Article

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