Design validation of .18 μm 1 GHz cache and register arrays

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 295-298

  Malone, Doug ^a   Bunce, Paul ^a   DellaPietro, Joe ^a   Davis, John ^a   Dawson, Jim ^a   Knips, Tom ^a   Plass, Don ^a   Pritzlaff, Phil ^a   Reyer, Ken ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); RANDOM ACCESS STORAGE; TIMING CIRCUITS;

CUSTOM REGISTER ARRAY; GIGAHERTZ DOMAIN COMPLEXITY; METAL COPPER TECHNOLOGY; PRODUCT LIKE CLOCKING; STACKED RANDOM ACCESS STORAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033683625     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)