A novel fault tolerant cache to improve yield in nanometer technologies

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 149-154

  Agarwal, Amit ^a   Paul, Bipul C ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN-SELF-TEST (BIST); FAULT TOLERANT CACHE; GAUSSIAN DISTRIBUTION; PROCESS PARAMETER VARIATIONS;

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; MATHEMATICAL MODELS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); PROBABILITY DENSITY FUNCTION; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 10444251734     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319673     Document Type: Conference Paper

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