Detection of trap generation in high-k gate stacks

IEEE International Integrated Reliability Workshop Final Report

Volumn 2005, Issue , 2005, Pages 79-83

  Young, C D ^a   Heh, D ^b   Nadkarni, S ^a   Choi, R ^a   Peterson, J J ^a   Harris, H R ^b   Sim, J H ^a   Krishnan, S A ^a   Barnett, J ^a   Vogel, E ^d   Lee, B H ^c   Zeitzoff, P ^a   Brown, G A ^a   Bersuker, G ^a  

^a SEMATECH   (United States)

^b AMD Assignee   (United States)

^c IBM   (United States)

^d NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; ELECTRIC POTENTIAL; RELIABILITY THEORY; SEMICONDUCTOR DEVICES; SILICON COMPOUNDS; TITANIUM DIOXIDE;

CHARGE PUMPING (CP); CONSTANT VOLTAGE STRESS (CVS); FREQUENCY-DEPENDENT DATA; VOLTAGE STRESS-INDUCED GENERATION;

ELECTRON TRAPS;

EID: 33847728664     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2005.1609568     Document Type: Conference Paper

References (18)

1. 2 thickness on charge trapping and mobility," Microelectronic Engineering, vol 80, pp. 218-221, 2005.
2. K. Takahashi, K. Manabe, A. Morioka, T. Ikarashi, T. Yoshihara, H. Watanabe, and T. Tatsumi, "High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics," presented at Intl. Conf. on Solid State Devices and Materials, Tokyo, Japan, pp. 22-23, 2004.
3. G. Bersuker, P. Zeitzoff, G. A. Brown, and H. R. Huff, "Dielectrics for Future Transistors," Materials Today, pp. 2633, 2004.
4. B. H. Lee, R. Choi, J. H. Sim, S. A. Krishnan, J. J. Peterson, G. A. Brown, and G. Bersuker, "Validity of constant voltage stress based reliability assessment of high-k devices," IEEE Transactions on Device and Materials Reliability, vol. 5, pp. 20-25, 2005.
5. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-k dielectrics reliability issues," IEEE Transactions on Device and Materials Reliability, vol. 5, pp. 5-19,2005.
6. G. Bersuker, J. Barnett, N. Moumen, B. Foran, C. D. Young, P. Lysaght, J. Peterson, B. H. Lee, P, M. Zetteoff, and H. R. Huff, "Interfacial layer-induced mobility degradation in high-k transistors," Jap. J. of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 43, pp. 7899-7902, 2004.
7. 2/TiN gate nMOS and pMOS transistors," presented at 43rd Annual IEEE Intl. Reliability Physics Symp. Proc, pp. 642-643, 2005.
8. 2 stack," presented at 42nd Annual IEEE Intl. Reliability Physics Symp. Proc., pp. 181-187, 2004.
9. 2 gate stacks with time dependent measurements," Microelectronics Reliability, vol. 45, pp. 806-810, 2005.
10. 2 reliability and yield," presented at IEEE Intl. Electron Devices Meeting Tech. Digest, pp. 38.5.1-38.5.4, 2003.
11. 2 dielectrics using charge pumping method," presented at 42nd Annual IEEE Intl. Reliability Physics Symp. Proc, pp. 581-582, 2004.
12. 2 gate dielectrics," presented at 41st Annual IEEE Intl. Reliability Physics Symp. Proc., pp. 41-45, 2003.
13. H. M. Bu and T. P. Ma, "Separating Interface Traps from Bulk Traps in High-k Gated MOSFETs Using Rise Time and Fall Time Dependence of Charge Pumping," as discussed at 35th IEEE Semiconductor Interface Specialists Conference, San Diego, CA, 2004.
14. J. H. Sim, R. Choi, Y. H. Lee, C. Young, P. Zeitzoff, D. L. Kwong, and G. Bersuker, "Trapping/de-trapping gate bias dependence of Hf-silicate dielectrics with poly and TiN gate electrode," Jap. J, of Applied Physics Part I-Regular Papers Short Notes & Review Papers, vol. 44, pp. 2420-2423,2005.
15. J. Barnett, C. D. Young, N. Moumen, and G. Bersuker, "Enhanced surface preparation techniques for the Si/high-k interface," in Ultra Clean Processing of Silicon Surfaces VIII, vol. 103-104, Solid State Phenomena, pp. 11-14, 2005.
16. J. R. Hauser and K. Ahmed, "Characterization of Ultrathin Oxides Using Electrical C-V and I-V Measurements," presented at Intl. Conf. on Characterization and Metrology for ULSI Technology, pp. 235-239, 1998.
17. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Transactions on Electron Devices, vol. 31, pp. 42-53, 1984.
18. Y. Maneglia and D. Bauza, "Extraction of slow oxide trap concentration profiles in metal-oxide-semiconductor transistors using the charge pumping method," Journal of Applied Physics, vol. 79, pp. 4187-4192, 1996.