-
1
-
-
0029516376
-
-
Tiwari S, Rana F, Chan K, Hanafi H, Chan W, Buchanan D. Volatile and non-volatile memories in Si with nano-crystal storage. IEDM-1995 Technical Digest 1995. p. 521-4.
-
-
-
-
2
-
-
0038781593
-
Nanocrystal nonvolatile memory devices
-
De Blauwe J. Nanocrystal nonvolatile memory devices. IEEE Trans Nanotechnol 1 (2002) 72-76
-
(2002)
IEEE Trans Nanotechnol
, vol.1
, pp. 72-76
-
-
De Blauwe, J.1
-
4
-
-
20344365310
-
-
Dimitrakis P, Normand P. Semiconductor nanocrystal floating-gate memory devices. In: Claverie A, Tsoukalas D, King T-J, Slaughter JM. Materials and processes for nonvolatile memories. Mater Res Soc Symp Proc 830, Warrendale: PA; 2005. p. D5.1.
-
-
-
-
6
-
-
33645731534
-
Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals
-
Ng C.Y., Chen T.P., Yang M., Yang J.B., Ding L., Li C.M., et al. Impact of programming mechanisms on the performance and reliability of nonvolatile memory devices based on Si nanocrystals. IEEE Trans Electron Devic 53 (2006) 663-667
-
(2006)
IEEE Trans Electron Devic
, vol.53
, pp. 663-667
-
-
Ng, C.Y.1
Chen, T.P.2
Yang, M.3
Yang, J.B.4
Ding, L.5
Li, C.M.6
-
7
-
-
17644429462
-
-
Muralidhar R, Steimle RF, Sadd M, Rao R, Swift CT, Prinz EJ, Yater J, Grieve L, Harber K, Hradsky B, Straub S, Acred B, Paulson W, Chen W, Parker L, Anderson SGH, Rossow M, Merchant T, Paransky M, Huynh T, Hadad D, Ko-Min Chang, White Jr BE. A 6 V Embedded 90 nm silicon nanocrystal nonvolatile memory. IEDM-2003 Technical Digest 2003. p. 601-4.
-
-
-
-
8
-
-
17644445363
-
-
De Salvo B, Gerardi C, Lombardo S, Baron T, Perniola L, Mariolle D, Mur P, Toffoli A, Gely M, Semeria MN, Deleonibus S, Ammendola G, Ancarani V, Melanotte M, Bez R, Baldi L, Corso D, Crupi I, Puglisi RA, Nicotra G, Rimini E, Mazen F, Ghibaudo G, Pananakakis G, Monzio Compagnoni C, Ielmini D, Lacaita A, Spinelli A, Wan YM, van der Jeugd K. How far will silicon nanocrystals push the scaling limits of NVMs technologies? IEDM-2003 Technical Digest, 2003. p. 597-600.
-
-
-
-
9
-
-
33646843945
-
Survey on Flash technology with specific attention to the critical process parameters related to manufacturing
-
Ginami G., Canali D., Fattori D., Girardi G., Scintu P., Tarchini L., and Tricarico D. Survey on Flash technology with specific attention to the critical process parameters related to manufacturing. Proc IEEE 91 (2003) 503-522
-
(2003)
Proc IEEE
, vol.91
, pp. 503-522
-
-
Ginami, G.1
Canali, D.2
Fattori, D.3
Girardi, G.4
Scintu, P.5
Tarchini, L.6
Tricarico, D.7
-
10
-
-
2442521364
-
Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact
-
Kim I.-G., Yanagidaira K., and Hiramoto T. Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact. IEEE Electron Device Lett 25 (2004) 265-267
-
(2004)
IEEE Electron Device Lett
, vol.25
, pp. 265-267
-
-
Kim, I.-G.1
Yanagidaira, K.2
Hiramoto, T.3
-
11
-
-
0032182598
-
Analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices
-
Lin S.C., Kuo J.B., Huang K.T., and Sun S.W. Analytical subthreshold current hump model for deep-submicron shallow-trench-isolated CMOS devices. Solid State Electron 42 (1998) 1871-1879
-
(1998)
Solid State Electron
, vol.42
, pp. 1871-1879
-
-
Lin, S.C.1
Kuo, J.B.2
Huang, K.T.3
Sun, S.W.4
-
12
-
-
0033225992
-
A review of narrow-channel effects for STI MOSFET's: a difference between surface- and buried-channel cases
-
Shigyo N., and Hiraoka T. A review of narrow-channel effects for STI MOSFET's: a difference between surface- and buried-channel cases. Solid State Electron 43 (1999) 2061-2066
-
(1999)
Solid State Electron
, vol.43
, pp. 2061-2066
-
-
Shigyo, N.1
Hiraoka, T.2
-
14
-
-
0032272978
-
-
Nandakumar M, Chatterjee A, Sridhar S, Joyner K, Rodder M, Chen I-C. Shallow trench isolation for advanced ULSI CMOS technologies. IEDM-1998 Technical Digest 1998. p. 133-6.
-
-
-
-
15
-
-
0033886157
-
Isolation edge effect depending on gate length of MOSFET's with isolation structures
-
Oishi T., Shiozawa K., Furukawa A., Abe Y., and Tokuda Y. Isolation edge effect depending on gate length of MOSFET's with isolation structures. IEEE Trans Elec Devic 47 (2000) 822-827
-
(2000)
IEEE Trans Elec Devic
, vol.47
, pp. 822-827
-
-
Oishi, T.1
Shiozawa, K.2
Furukawa, A.3
Abe, Y.4
Tokuda, Y.5
-
16
-
-
33846785854
-
-
Isler M, Schley J-M, Riedel S, Mikolajick T, Ludwig C, Kuesters K-H, Tempel G, Sachse J-U, Deconinck P, Mikalo R, Reichelt R, Schulse N, Stein v. Kamienski E, Strassburg M, Willer J, Lau F, Hagenbeck R, Haibach P. STI engineering for high program and erase performance of STI-bounded nitride storage flash memory cells. ICMTD 2005, PF-7. Giens: France; 2005.
-
-
-
-
17
-
-
0030287695
-
Analysis of width edge effects in advanced isolation schemes for deep-submicron CMOS technologies
-
Sallagoity P., Ada-Hanifi M., Paoli M., and Haond M. Analysis of width edge effects in advanced isolation schemes for deep-submicron CMOS technologies. IEEE Trans Elec Devic 4 (1996) 1900-1906
-
(1996)
IEEE Trans Elec Devic
, vol.4
, pp. 1900-1906
-
-
Sallagoity, P.1
Ada-Hanifi, M.2
Paoli, M.3
Haond, M.4
-
18
-
-
3943104812
-
Effect of capping silicon nitride layer and nitrided gate oxide on hump of transistors
-
Park W.K., Lee J.H., and Lim G. Effect of capping silicon nitride layer and nitrided gate oxide on hump of transistors. IEEE Elec Devic Lett 25 (2004) 532-534
-
(2004)
IEEE Elec Devic Lett
, vol.25
, pp. 532-534
-
-
Park, W.K.1
Lee, J.H.2
Lim, G.3
-
19
-
-
2942648428
-
Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis
-
Dimitrakis P., Kapetanakis E., Tsoukalas D., Skarlatos D., Bonafos C., Ben Asssayag G., et al. Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis. Solid State Electron 48 (2004) 1511-1517
-
(2004)
Solid State Electron
, vol.48
, pp. 1511-1517
-
-
Dimitrakis, P.1
Kapetanakis, E.2
Tsoukalas, D.3
Skarlatos, D.4
Bonafos, C.5
Ben Asssayag, G.6
-
20
-
-
2542488754
-
Processing issues in silicon nanocrystal manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications
-
Normand P., Dimitrakis P., Kapetanakis E., Skarlatos D., Beltsios K., Tsoukalas D., Bonafos C., Coffin H., Benassayag G., Claverie A., Soncini V., Agarwal A., Soh Ch., and Ameen M. Processing issues in silicon nanocrystal manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications. Microelectron Eng 73-74 (2004) 730-735
-
(2004)
Microelectron Eng
, vol.73-74
, pp. 730-735
-
-
Normand, P.1
Dimitrakis, P.2
Kapetanakis, E.3
Skarlatos, D.4
Beltsios, K.5
Tsoukalas, D.6
Bonafos, C.7
Coffin, H.8
Benassayag, G.9
Claverie, A.10
Soncini, V.11
Agarwal, A.12
Soh, Ch.13
Ameen, M.14
-
21
-
-
0034454561
-
-
Ishii T, OsabeT, MineT, Murai F, Yano K. Engineering variations: towards practical single-electron (few-electron) memory. IEDM-2000 Technical Digest, 2000. p. 305-8.
-
-
-
-
22
-
-
2442618926
-
AMS depth profiling of humidity in silica
-
Pilz W., Friedrich M., Heinig K.-H., Schmidt B., and von Borany J. AMS depth profiling of humidity in silica. Nuclear Inst Meth Phys Res B 219/220 (2004) 459-462
-
(2004)
Nuclear Inst Meth Phys Res B
, vol.219-220
, pp. 459-462
-
-
Pilz, W.1
Friedrich, M.2
Heinig, K.-H.3
Schmidt, B.4
von Borany, J.5
-
23
-
-
0023422261
-
Modeling of transconductance degradation and extraction of threshold-voltage in thin oxide MOSFET's
-
Wong H.S., White M.H., Krutsick T.J., and Booth R.V. Modeling of transconductance degradation and extraction of threshold-voltage in thin oxide MOSFET's. Solid State Electron 30 (1987) 953-968
-
(1987)
Solid State Electron
, vol.30
, pp. 953-968
-
-
Wong, H.S.1
White, M.H.2
Krutsick, T.J.3
Booth, R.V.4
-
24
-
-
0036540852
-
A review of recent MOSFET threshold-voltage extraction methods
-
Ortiz-Conde A., Garcia Sanchez F.J., Liou J.J., Cerdeira A., Estrada M., and Yue Y. A review of recent MOSFET threshold-voltage extraction methods. Microelectron Reliab 42 (2002) 583-596
-
(2002)
Microelectron Reliab
, vol.42
, pp. 583-596
-
-
Ortiz-Conde, A.1
Garcia Sanchez, F.J.2
Liou, J.J.3
Cerdeira, A.4
Estrada, M.5
Yue, Y.6
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