Isolation edge effect depending on gate length of MOSFET's with various isolation structures

IEEE Transactions on Electron Devices

Volumn 47, Issue 4, 2000, Pages 822-827

  Oishi, Toshiyuki ^a   Shiozawa, Katsuomi ^a   Furukawa, Akihiko ^a   Abe, Yuji ^a   Tokuda, Yasunori ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; OXIDATION; SEMICONDUCTING SILICON;

ISOLATION EDGE EFFECTS; LOCAL OXIDATION OF SILICON (LOCOS); SHORT CHANNEL EFFECTS (SCE);

MOSFET DEVICES;

EID: 0033886157     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.830999     Document Type: Article

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