Floorplanning with wire pipelining in adaptive communication channels

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2996-3004

  Casu, Mario R ^a   Macchiarulo, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b University of Hawaii at Manoa   (United States)

Author keywords

Floorplanning; Systems on chip; Wire pipelining (WP)

Indexed keywords

BENCHMARKING; COMMUNICATION CHANNELS (INFORMATION THEORY); DATA TRANSFER; DELAY CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION;

BLOCK DELAY; FLOORPLANNING; SYSTEMS ON CHIPS; WIRE PIPELINING (WP);

WIRE;

EID: 33845601325     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882590     Document Type: Article

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