Hardware/software concurrent design for a real-time SPML MPEG2 video-encoder chip set

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 320-326

  Ikeda, Mitsuo ^a   Okubo, Tsuneo ^a   Abe, Tetsuya ^a   Ito, Yoshinori ^a   Tashiro, Yutaka ^a   Kasai, Ryota ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; IMAGE COMPRESSION; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SOFTWARE ENGINEERING;

HARDWARE/SOFTWARE CONCURRENT DESIGN; MOTION PICTURE EXPERTS GROUP STANDARD 2; VIDEO ENCODER CHIP SET;

IMAGE CODING;

EID: 0029755803     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)