Processing rate optimization by sequential system floorplanning

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 340-345

  Wang, Jia ^a   Wu, Ping Chih ^b   Zhou, Hai ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL INTERCONNECTS; HIGHER FREQUENCIES; INTERCONNECT DELAY; LATENCY-INSENSITIVE DESIGNS; PERFORMANCE MEASURE; PROCESSING RATES; SEQUENTIAL SYSTEMS; WIRE PIPELINING;

DESIGN; INTERCONNECTION NETWORKS;

OPTIMIZATION;

EID: 33845628536     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.108     Document Type: Conference Paper

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