Floorplan assisted data rate enhancement through wire pipelining: A real assessment

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2005, Pages 121-128

  Casu, Mario R ^a   Macchiarulo, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b University of Hawaii at Manoa   (United States)

Author keywords

Floorplanning; Systems on chip; Throughput; Wire pipelining

Indexed keywords

DATA TRANSFER; DELAY CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; TECHNOLOGY TRANSFER;

FLOORPLANNING; SYSTEMS-ON-CHIP; WIRE PIPELINING;

ELECTRIC WIRE;

EID: 29144457433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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