Two orders of magnitude leakage power reduction of low voltage SRAM's by row-by-row dynamic VDD control (RRDV) scheme

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 381-385

  Kanda, Kouichi ^a   Miyazaki, Takayuki ^a   Sik, Mitt Kyeong ^a   Kawaguchi, Hiroshi ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CELLS; CYTOLOGY; SEMICONDUCTOR STORAGE;

DRAIN INDUCED BARRIER LOWERING EFFECTS; FUTURE GENERATIONS; LEAKAGE POWER REDUCTION; LOW VOLTAGE REGION; LOW-VOLTAGE SRAM; NEGATIVE VOLTAGE; ORDERS OF MAGNITUDE; SUPPLY VOLTAGES;

STATIC RANDOM ACCESS STORAGE;

EID: 84949447485     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158089     Document Type: Conference Paper

References (5)

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3. K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, and T. Kuroda, "A 300MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable VTH CMOS," Custom Integrated Circuits Conference, pp.587-590, May 1997.
4. K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, "A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM's," Symposium on VLSI circuits, pp.70-71, June 2000.
5. S. Hattori, and T. Sakurai, "90% Write Power Saving SRAM Using Sense-Amplifying Memory Cell," Symposium on VLSI circuits, pp.46-47, June 2002.