16.7-fA/Cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1952-1957

  Osada, Kenichi ^a   Saitoh, Yoshikazu ^b   Ibe, Eishi ^a   Ishibashi, Koichiro ^c  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c STARC   (Japan)

Author keywords

Cosmic ray; Error checking and correction (ECC); Gate tunnel leakage; Low standby current; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; COSMIC RAYS; ELECTRIC CURRENT CONTROL; ELECTRIC FIELDS; ELECTRON TUNNELING; ERROR CORRECTION; ERRORS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; MOS DEVICES; TECHNOLOGICAL FORECASTING;

COSMIC-RAY-INDUCED MULTIERRORS; ELECTRIC FIELD RELAXATION SCHEME; ERROR CHECKING AND CORRECTION; TUNNEL LEAKAGE CURRENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 0242468185     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818138     Document Type: Article

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