Mixed PLB and interconnect BIST for FPGAs without fault-free assumptions

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 36-41

  Suthar, Vishal ^a   Dutt, Shantanu ^a  

^a University of Illinois at Chicago   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT-FREE; FAULT-FREE TEST CIRCUIT; NANOMETER TECHNOLOGIES;

BUILT-IN SELF TEST; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; ITERATIVE METHODS; PROBLEM SOLVING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33751087543     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.47     Document Type: Conference Paper

References (16)

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