Bist-Diagnosis of Interconnect Fault Locations in FPGA's

Canadian Conference on Electrical and Computer Engineering

Volumn 1, Issue , 2003, Pages 207-210

  Liu, J ^a   Simmons, S ^a  

^a QUEEN S UNIVERSITY   (Canada)

Author keywords

Fault Detection; Fault Diagnosis; FPGA; Interconnect

Indexed keywords

BUILT-IN SELF TEST; COMPUTER AIDED DESIGN; FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; RANDOM ACCESS STORAGE;

FAULT DIAGNOSIS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0141565204     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. X. Sun, S. Xu, J. Xu and P. Trouborst, "Design and Implementation of a Parity-Based BIST Scheme for FPGA Global Interconnects", CCECE 2001.
4. th ACM International symposium on FPGA 1998, pp 95-104
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