Design optimization for robustness to single-event upsets

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 202-207

  Zhou, Quming ^a   Choudhury, Mihir R ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

OPTIMIZATION ALGORITHMS; PERFORMANCE CONSTRAINTS; SINGLE EVENT UPSETS (SEU);

ALGORITHMS; COMPUTATIONAL GEOMETRY; CONSTRAINT THEORY; LOGIC GATES; MATHEMATICAL MODELS; SYSTEMS ANALYSIS;

ROBUSTNESS (CONTROL SYSTEMS);

EID: 33751081578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.28     Document Type: Conference Paper

References (23)

1. J. F. Ziegler et al., "IBM experiments in soft fails in computer electronics (1978-1994)," IBM Journal of Research and Development, vol. 40, pp. 3-18, Jan. 1996.
2. R. W. Keyes, "Fundamental limits of silicon technology," Proc. of the IEEE, vol. 89, pp. 227-239, Mar. 2001.
3. D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," in Proc. Intl. Reliability Physics Symposium, pp. 216-225, 2002.
4. H. H. K. Tang and K. P. Rodbell, "Single-event upsets in microelectronics: fundamental physics and issues," Materials Research Society Bulletin, vol. 28, pp. 111-116, Feb. 2003.
5. R. Baumann, "Soft errors in advanced computer systems," IEEE Design and Test of Computers, vol. 22, pp. 258-266, May 2004.
6. M. Nicolaidis and Y. Zorian, "On-line testing for vlsi-a compendium of approaches," vol. 12, pp. 7-20, Feb.-Apr. 1998.
7. S. Mitra et al., "Robust system design with built-in soft error resilience," IEEE Computer, vol. 38, pp. 43-52, Feb. 2005.
8. J. M. Cazeaux et al., "On transistor level gate sizing for increased robustness to transient faults," in Proc. Intl. On-line Testing Symposium, pp. 23-28, 2005.
9. Y. S. Dhillon, A. U. Diril, and A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," in Proc. Design Automation and Test in Europe, pp. 288-293, 2005.
10. C. Zhao, Y. Zhao, and S. Dey, "Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits," in Proc. Design Automation Conference, pp. 190-195, 2005.
11. Q. Zhou and K. Mohanram, "Gate sizing to radiation harden combinational logic," IEEE Trans. Computer-aided Design, vol. 25, pp. 155-166, Jan. 2006.
12. R. Murgai, "Technology-based transformations," in Logic synthesis and verification (S. Hassoun, T. Sasao, and R. K. Brayton, eds.), ch. 6, Kluwer Academic Publishers, Boston, MA, 2002.
13. S. Boyd et al., "Digital circuit optimization via geometric programming," Operations Research, vol. 53, pp. 899-932, Nov.-Dec. 2005.
14. G. C. Messenger, "Collection of charge on junction nodes from ion tracks," IEEE Trans. Nuclear Science, vol. 29, pp. 2024-2031, Dec. 1982.
15. A. Dharchoudhury, S. M. Kang, H. Cha, and J. H. Patel, "Fast timing simulation of transient faults in digital circuits," in Proc. Intl. Conference Computer-aided Design, pp. 719-726, 1994.
16. Y. H. Shih and S. M. Kang, "Analytic transient solution of general MOS circuit primitives," IEEE Trans. Computer-aided Design, vol. 11, pp. 719-731, Jun. 1992.
17. P. Dahlgren and P. Lidén, "A switch-level algorithm for simulation of transients in combinational logic," in Proc. Intl. Fault-tolerant Computing Symposium, pp. 207-216, 1995.
18. K. Mohanram, "Closed-form simulation and robustness models for SEU-tolerant design," in Proc. VLSI Test Symposium, pp. 327-333, 2005.
19. J. P. Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. Intl. Conference Computer-aided Design, pp. 326-328, 1985.
20. "MOSEK ApS." Please visit the URL http://www.mosek.com/ for further details.
21. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. Custom Integrated Circuits Conference, pp. 201-204, 2000.
22. S. Yang, "Logic synthesis and optimization benchmarks user guide," tech. rep., MCNC, Research Triangle Park, 1991.
23. K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proc. Intl. Test Conference, pp. 893-901, 2003.