Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 190-195

  Zhao, Chong ^a   Zhao, Yi ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit hardening; Nanometer circuits; Robustness calibration; Robustness insertion

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DIGITAL CIRCUITS; ESTIMATION; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

CIRCUIT HARDENING; NANOMETER CIRCUITS; ROBUSTNESS CALIBRATION; ROBUSTNESS INSERTION;

VLSI CIRCUITS;

EID: 27944505953     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065631     Document Type: Conference Paper

References (15)

1. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2001
2. J. Cong, D. Z. Pan, and P. V. Srinivas, "Improved crosstalk modeling for noise constrained interconnect optimization," Proc. ASP-DAC,pp. 373-378, 2001.
3. Shen Lin, Chang N., "Challenges in power-ground integrity," Proc. ICCAD'01,pp. 651-644, 2001.
4. J.-J. Liou, A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 756-769, Jun. 2003.
5. Hess C, Stine BE, Weiland LH, Sawada K., "Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits," Intl. Conf. Microelectronic Test Structures, pp. 189-196, 2002.
6. Peter Hazucha, Christer Svensson, "Cosmic-Ray Soft Error Rate Characterization of a Standard 0.6-μm CMOS Process." IEEE Jnl. Solid-State Circuits, vol. 35, no. 10, Oct. 2000.
7. Anghel, L., Nicolaidis, M., "Cost Reduction and Evaluation of a Temporary Faults Detecting Technique," DATE'00, pp. 591-598, 2000.
8. E. Dupont, M. Nicolaidis, and P. Rohr, "Embedded Robustness IPs for Transient-Error-Free ICs," IEEE Design & Test of Computers, pp.56-10, May-June, 2002.
9. Y. Zhao, S. Dey, "Separate Dual Transistor Register-an Circuit Solution for on-line Testing of Transient Errors in UDSM-IC," Proc. IOLTS. 2003, pp.7-11, 2003.
10. C.Zhao, X. Bai, S.Dey, "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," in Proc. DAC'04, pp. 894-899, 2004.
11. C.Zhao, X. Bai, S.Dey, "A Static Noise-Impact-Analysis Methodology for Evaluating Transient Error Effects in Digital VLSI Circuits", Research Report, http://esdat.ucsd.edu/~chong/nia.pdf.
12. T. C. Hu and M. T. Shing, Combinatorial Algorithms, Dover Publications, Inc., pp.111-113, 2002.
13. T. H. Cormen, C. E. Leiserson, R. L. Rivest and C. Stein, "Introduction to Algorithms", Ch 15, McGraw-Hill, 1990.
14. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," Proc. VTS, pp. 86-94, 1999.
15. http://www.tensilica.com/xtensa_overview_handbook.pdf, Xtensa™ Microprocessor Overview Handbook, Tensilica Inc, August 2001