Back side exposure of variable size through silicon vias

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 24, Issue 5, 2006, Pages 2460-2466

  Rowbotham, T ^a   Patel, J ^a   Lam, T ^a   Abhulimen, I U ^a   Burkett, S ^a   Cai, L ^a   Schaper, L ^a  

^a 3202 Bell Engineering Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROSCALE VERTICAL INTERCONNECTS; SILICON ETCH; SILICON VIAS; WAFER GRINDING;

ELECTRIC CONTACTS; ELECTRIC INSULATION; ELECTROPLATING; INTERCONNECTION NETWORKS; REACTIVE ION ETCHING;

SILICON WAFERS;

EID: 33749320317     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.2221313     Document Type: Article

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