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Journal of Materials Science: Materials in Electronics

Volumn 17, Issue 9, 2006, Pages 711-722

Surface roughness and interface engineering for gate dielectrics on strained layers

(4) Maiti, C K a Samanta, S K a Bera, M K a Chattopadhyay, Sanatan a,b

a INDIAN INSTITUTE OF TECHNOLOGY (India)

b NEWCASTLE UNIVERSITY (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); MORPHOLOGY; OXIDATION; SEMICONDUCTING SILICON COMPOUNDS; SUBSTRATES; SURFACE ROUGHNESS; TRANSMISSION ELECTRON MICROSCOPY;

GATE DIELECTRICS; OXIDATION RATE; SILICON COMPOUNDS SUBSTRATES; STRAINED LAYERS;

MIS DEVICES;

EID: 33749250726 PISSN: 09574522 EISSN: 1573482X Source Type: Journal
DOI: 10.1007/s10854-006-0023-2 Document Type: Article

Times cited : (4)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.